step_motor_degree_forward_reverse_lcd.syr

將正在順時針或逆時針旋轉的步進馬達目前角度顯示在ＬＣＭ上。

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: step_motor_degree_forward_reverse_lcd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : step_motor_degree_forward_reverse_lcd.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : step_motor_degree_forward_reverse_lcd
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : step_motor_degree_forward_reverse_lcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : step_motor_degree_forward_reverse_lcd.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
WARNING:HDLParsers:3215 - Unit work/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_4DIG is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_4DIG/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_1DIG is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_SUB_1DIG/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_1DIG is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD
WARNING:HDLParsers:3215 - Unit work/BCD_ADD_1DIG/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD
WARNING:HDLParsers:3215 - Unit work/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD
WARNING:HDLParsers:3215 - Unit work/BIN_ADD_4BIT is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD
WARNING:HDLParsers:3215 - Unit work/BIN_ADD_4BIT/BIN_ADD_4BIT_ARCH is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD
WARNING:HDLParsers:3215 - Unit work/COMPLEMENT is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd
WARNING:HDLParsers:3215 - Unit work/COMPLEMENT/BEHAVIORAL is now defined in a different file: was C:/BOOK_ISE/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd, now is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD_PACK.VHD in Library work.
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD in Library work.
Entity <BIN_ADD_4BIT> (Architecture <BIN_ADD_4BIT_arch>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd in Library work.
Entity <COMPLEMENT> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD in Library work.
Entity <BCD_ADD_1DIG> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd in Library work.
Entity <BCD_ADD_SUB_1DIG> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD in Library work.
Entity <BCD_ADD_SUB_4DIG> (Architecture <Behavioral>) compiled.
Compiling vhdl file C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD in Library work.
Entity <STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <step_motor_degree_forward_reverse_lcd> (Architecture <Behavioral>).
INFO:Xst:1304 - Contents of register <LCM_RW> in unit <step_motor_degree_forward_reverse_lcd> never changes during circuit operation. The register is replaced by logic.
Entity <step_motor_degree_forward_reverse_lcd> analyzed. Unit <step_motor_degree_forward_reverse_lcd> generated.

Analyzing Entity <BCD_ADD_SUB_4DIG> (Architecture <behavioral>).
Entity <BCD_ADD_SUB_4DIG> analyzed. Unit <BCD_ADD_SUB_4DIG> generated.

Analyzing Entity <BCD_ADD_SUB_1DIG> (Architecture <behavioral>).
Entity <BCD_ADD_SUB_1DIG> analyzed. Unit <BCD_ADD_SUB_1DIG> generated.

Analyzing Entity <COMPLEMENT> (Architecture <behavioral>).
Entity <COMPLEMENT> analyzed. Unit <COMPLEMENT> generated.

Analyzing Entity <BCD_ADD_1DIG> (Architecture <behavioral>).
WARNING:Xst:753 - C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD line 31: Unconnected output port 'CARRY' of component 'BIN_ADD_4BIT'.
Entity <BCD_ADD_1DIG> analyzed. Unit <BCD_ADD_1DIG> generated.

Analyzing Entity <BIN_ADD_4BIT> (Architecture <bin_add_4bit_arch>).
Entity <BIN_ADD_4BIT> analyzed. Unit <BIN_ADD_4BIT> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <BIN_ADD_4BIT>.
    Related source file is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BIN_ADD_4BIT.VHD.
    Found 4-bit xor3 for signal <SUM>.
    Summary:
	inferred   4 Xor(s).
Unit <BIN_ADD_4BIT> synthesized.


Synthesizing Unit <BCD_ADD_1DIG>.
    Related source file is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_1DIG.VHD.
Unit <BCD_ADD_1DIG> synthesized.


Synthesizing Unit <COMPLEMENT>.
    Related source file is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/COMPLEMENT.vhd.
    Found 1-bit xor2 for signal <$n0001> created at line 25.
    Found 3 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   3 Multiplexer(s).
Unit <COMPLEMENT> synthesized.


Synthesizing Unit <BCD_ADD_SUB_1DIG>.
    Related source file is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_1DIG.vhd.
Unit <BCD_ADD_SUB_1DIG> synthesized.


Synthesizing Unit <BCD_ADD_SUB_4DIG>.
    Related source file is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/BCD_ADD_SUB_4DIG.VHD.
WARNING:Xst:646 - Signal <CT<4>> is assigned but never used.
Unit <BCD_ADD_SUB_4DIG> synthesized.


Synthesizing Unit <step_motor_degree_forward_reverse_lcd>.
    Related source file is C:/DMATEK_BOOK/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD/STEP_MOTOR_DEGREE_FORWARD_REVERSE_LCD.VHD.
    Found 1-bit register for signal <LCM_RS>.
    Found 8-bit register for signal <LCM_DATA>.
    Found 6-bit comparator less for signal <$n0011> created at line 65.
    Found 6-bit adder for signal <$n0019> created at line 66.
    Found 16-bit register for signal <DEGREE>.
    Found 25-bit up counter for signal <DIVIDER>.
    Found 6-bit register for signal <LCM_COUNT>.
    Found 4-bit register for signal <PATTERN>.
    Found 5 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
	inferred   5 Multiplexer(s).
Unit <step_motor_degree_forward_reverse_lcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  6-bit register                   : 1
  1-bit register                   : 1
  8-bit register                   : 1
  4-bit register                   : 1
  16-bit register                  : 1
# Counters                         : 1
  25-bit up counter                : 1
# Multiplexers                     : 14
  2-to-1 multiplexer               : 14
# Adders/Subtractors               : 1
  6-bit adder                      : 1
# Comparators                      : 1
  6-bit comparator less            : 1
# Xors                             : 36
  1-bit xor2                       : 4
  1-bit xor3                       : 32

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <step_motor_degree_forward_reverse_lcd> ...

Optimizing unit <BIN_ADD_4BIT> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <DEGREE_0> (without init value) is constant in block <step_motor_degree_forward_reverse_lcd>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block step_motor_degree_forward_reverse_lcd, actual ratio is 4.
FlipFlop LCM_COUNT_3 has been replicated 1 time(s)
FlipFlop LCM_COUNT_1 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : step_motor_degree_forward_reverse_lcd.ngr
Top Level Output File Name         : step_motor_degree_forward_reverse_lcd
Output Format                      : NGC