📄 step_motor_degree_forward_reverse_lcd.mrp
字号:
Release 6.1.03i Map G.26Xilinx Mapping Report File for Design 'step_motor_degree_forward_reverse_lcd'Design Information------------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-pq208-5 -cm
area -pr b -k 4 -c 100 -tx off -o step_motor_degree_forward_reverse_lcd_map.ncd
step_motor_degree_forward_reverse_lcd.ngd
step_motor_degree_forward_reverse_lcd.pcf Target Device : x2s200Target Package : pq208Target Speed : -5Mapper Version : spartan2 -- $Revision: 1.16 $Mapped Date : Tue Jan 06 12:45:31 2004Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 53 out of 4,704 1% Number of 4 input LUTs: 186 out of 4,704 3%Logic Distribution: Number of occupied Slices: 111 out of 2,352 4% Number of Slices containing only related logic: 111 out of 111 100% Number of Slices containing unrelated logic: 0 out of 111 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 215 out of 4,704 4% Number used as logic: 186 Number used as a route-thru: 29 Number of bonded IOBs: 17 out of 140 12% IOB Flip Flops: 8 Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 1,787Additional JTAG gate count for IOBs: 864Peak Memory Usage: 62 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| CLK | GCLKIOB | INPUT | LVTTL | | | | | || DIRECTION | IOB | INPUT | LVTTL | | | | | || LCM_DATA<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_DATA<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || LCM_EN | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LCM_RS | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || LCM_RW | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || RESET | IOB | INPUT | LVTTL | | | | | || TRIGGER<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || TRIGGER<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || TRIGGER<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || TRIGGER<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 18Number of Equivalent Gates for Design = 1,787Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 24IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 8Unbonded IOBs = 0Bonded IOBs = 17Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 34 input LUTs used as Route-Thrus = 294 input LUTs = 186Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 24Slice Flip Flops = 53Slices = 111Number of LUT signals with 4 loads = 2Number of LUT signals with 3 loads = 12Number of LUT signals with 2 loads = 21Number of LUT signals with 1 load = 140NGM Average fanout of LUT = 1.68NGM Maximum fanout of LUT = 17NGM Average fanin for LUT = 3.5161Number of LUT symbols = 186Number of IPAD symbols = 3Number of IBUF symbols = 2⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -