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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    DECODER.vhd
Scanning    CLOCK_PACK.vhd
Scanning    DECODER.vhd
Writing DECODER.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_00_23.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_00_23.VHD
Writing COUNT_00_23.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_0_5.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_0_5.VHD
Writing COUNT_0_5.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_0_9.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_0_9.VHD
Writing COUNT_0_9.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/CLOCK_PACK.vhd in Library work.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD in Library work.
Entity <count_0_9> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD in Library work.
Entity <count_0_5> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD in Library work.
Entity <clk_set> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD in Library work.
Entity <count_00_59> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD in Library work.
Entity <count_00_23> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/DECODER.vhd in Library work.
Entity <decoder> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD in Library work.
Entity <segment_scan_clock_24> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <segment_scan_clock_24> (Architecture <behavioral>).
Entity <segment_scan_clock_24> analyzed. Unit <segment_scan_clock_24> generated.

Analyzing Entity <clk_set> (Architecture <behavioral>).
Entity <clk_set> analyzed. Unit <clk_set> generated.

Analyzing Entity <count_00_59> (Architecture <behavioral>).
Entity <count_00_59> analyzed. Unit <count_00_59> generated.

Analyzing Entity <count_00_23> (Architecture <behavioral>).
Entity <count_00_23> analyzed. Unit <count_00_23> generated.

Analyzing Entity <decoder> (Architecture <behavioral>).
Entity <decoder> analyzed. Unit <decoder> generated.

Analyzing Entity <count_0_9> (Architecture <behavioral>).
Entity <count_0_9> analyzed. Unit <count_0_9> generated.

Analyzing Entity <count_0_5> (Architecture <behavioral>).
Entity <count_0_5> analyzed. Unit <count_0_5> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count_0_5>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD.
    Found 4-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
Unit <count_0_5> synthesized.


Synthesizing Unit <count_0_9>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD.
    Found 4-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
Unit <count_0_9> synthesized.


Synthesizing Unit <decoder>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/DECODER.vhd.
Unit <decoder> synthesized.


Synthesizing Unit <count_00_23>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD.
    Found 4-bit adder for signal <$n0000> created at line 32.
    Found 4-bit adder for signal <$n0001> created at line 34.
    Found 8-bit register for signal <time_bcd>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <count_00_23> synthesized.


Synthesizing Unit <count_00_59>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD.
Unit <count_00_59> synthesized.


Synthesizing Unit <clk_set>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD.
    Found 25-bit up counter for signal <divider>.
    Summary:
	inferred   1 Counter(s).
Unit <clk_set> synthesized.


Synthesizing Unit <segment_scan_clock_24>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD.
WARNING:Xst:737 - Found 4-bit latch for signal <decoder_bcd>.
    Found 6-bit register for signal <position>.
Unit <segment_scan_clock_24> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 9
  1-bit register                   : 8
  6-bit register                   : 1
# Latches                          : 1
  4-bit latch                      : 1
# Counters                         : 5
  4-bit up counter                 : 4
  25-bit up counter                : 1
# Adders/Subtractors               : 2
  4-bit adder                      : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <segment_scan_clock_24> ...

Optimizing unit <decoder> ...

Optimizing unit <count_00_23> ...

Mapping all equations...
WARNING:Xst:637 - Naming conflict between signal bcd<3> of unit decoder and signal decoder_bcd<3> of unit segment_scan_clock_24 : renaming decoder_bcd<3> to decoder_bcd<3>1.
WARNING:Xst:637 - Naming conflict between signal bcd<2> of unit decoder and signal decoder_bcd<2> of unit segment_scan_clock_24 : renaming decoder_bcd<2> to decoder_bcd<2>1.
WARNING:Xst:637 - Naming conflict between signal bcd<0> of unit decoder and signal decoder_bcd<0> of unit segment_scan_clock_24 : renaming decoder_bcd<0> to decoder_bcd<0>1.
WARNING:Xst:637 - Naming conflict between signal bcd<1> of unit decoder and signal decoder_bcd<1> of unit segment_scan_clock_24 : renaming decoder_bcd<1> to decoder_bcd<1>1.
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block segment_scan_clock_24, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      61  out of   2352     2%  
 Number of Slice Flip Flops:            59  out of   4704     1%  
 Number of 4 input LUTs:                99  out of   4704     2%  
 Number of bonded IOBs:                 15  out of    144    10%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
_n003021:o                         | NONE(*)(decoder_bcd_1_0)| 4     |
clk                                | BUFGP                  | 25    |
time_base_divider_24:q             | NONE                   | 24    |
time_base_divider_15:q             | NONE                   | 6     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.587ns (Maximum Frequency: 94.455MHz)
   Minimum input arrival time before clock: 7.000ns
   Maximum output required time after clock: 10.731ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -quiet -dd c:\hardware\segment_scan_clock_24/_ngo -uc
SEGMENT_SCAN_CLOCK_24CF.ucf -insert_keep_hierarchy -p xc2s200-pq208-5
segment_scan_clock_24.ngc segment_scan_clock_24.ngd 

Reading NGO file "C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/segment_scan_clock_24.ngc"
...
Reading component libraries for design expansion...

Annotating constraints to design from file "SEGMENT_SCAN_CLOCK_24CF.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "segment_scan_clock_24.ngd" ...

Writing NGDBUILD log file "segment_scan_clock_24.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Map".

Using target part "2s200pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
   Number of errors:      0
   Number of warnings:    1
   Number of Slices:                 64 out of  2,352    2%
   Number of Slices containing
      unrelated logic:                0 out of     64    0%
   Total Number Slice Registers:     59 out of  4,704    1%
      Number used as Flip Flops:                   55
      Number used as Latches:                       4
   Total Number 4 input LUTs:        95 out of  4,704    2%
      Number used as LUTs:                         68
      Number used as a route-thru:                 27
   Number of bonded IOBs:            15 out of    140   10%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
Total equivalent gate count for design:  1,144
Additional JTAG gate count for IOBs:  768
Peak Memory Usage:  56 MB

Mapping completed.
See MAP report file "segment_scan_clock_24_map.mrp" for details.

Completed process "Map".

Mapping Module segment_scan_clock_24 . . .
MAP command line:
map -quiet -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o segment_scan_clock_24_map.ncd segment_scan_clock_24.ngd segment_scan_clock_24.pcf
Mapping Module segment_scan_clock_24: DONE



Started process "Place & Route".

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.




Constraints file: segment_scan_clock_24.pcf

Loading device database for application par from file
"segment_scan_clock_24_map.ncd".
   "segment_scan_clock_24" is an NCD, version 2.37, device xc2s200, package
pq208, speed -5
Loading device for application par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRELIMINARY 1.25 2002-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            15 out of 140    10%
      Number of LOCed External IOBs   15 out of 15    100%

   Number of SLICEs                   64 out of 2352    2%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98981c) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.......