__projnav.log

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....
Phase 5.8 (Checksum:99a902) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file segment_scan_clock_24.ncd.

Total REAL time to placer completion: 0 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 409 unrouted;       REAL time: 2 secs 

Phase 2: 359 unrouted;       REAL time: 24 secs 

Phase 3: 99 unrouted; (~0)      REAL time: 24 secs 

Phase 4: 99 unrouted; (~0)      REAL time: 24 secs 

Phase 5: 99 unrouted; (~0)      REAL time: 24 secs 

Phase 6: 0 unrouted; (~0)      REAL time: 24 secs 

Finished Router          REAL time: 24 secs 

Total REAL time to router completion: 25 secs 
Total CPU time to router completion: 24 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_bufgp          |  Global  |   13   |  0.000     |  0.750      |
+----------------------------+----------+--------+------------+-------------+
|   time_base_divider<24>    |Low-Skew  |   18   |  0.834     |  5.420      |
+----------------------------+----------+--------+------------+-------------+
|   time_base_divider<15>    |Low-Skew  |    5   |  0.126     |  5.279      |
+----------------------------+----------+--------+------------+-------------+
|            _n0030          |Low-Skew  |    4   |  0.333     |  5.037      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HI | 25.000ns   | 10.521ns   | 6    
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.

All signals are completely routed.

Total REAL time to par completion: 25 secs 
Total CPU time to par completion: 24 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file segment_scan_clock_24.ncd.


PAR done.

Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Loading device database for application trce.exe from file
"segment_scan_clock_24.ncd".
   "segment_scan_clock_24" is an NCD, version 2.37, device xc2s200, package
pq208, speed -5
Loading device for application trce.exe from file 'v200.nph' in environment
C:/Xilinx.

Analysis completed Tue May 06 14:10:55 2003
--------------------------------------------------------------------------------

Generating Report ...


Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module segment_scan_clock_24 . . .
PAR command line: par -w -ol 2 -t 1 segment_scan_clock_24_map.ncd segment_scan_clock_24.ncd segment_scan_clock_24.pcf
PAR completed successfully




Started process "Generate Programming File".

Release 5.1i - Bitgen F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Loading device database for application Bitgen from file
"segment_scan_clock_24.ncd".
   "segment_scan_clock_24" is an NCD, version 2.37, device xc2s200, package
pq208, speed -5
Loading device for application Bitgen from file 'v200.nph' in environment
C:/Xilinx.
Opened constraints file segment_scan_clock_24.pcf.

Tue May 06 14:10:57 2003

Running DRC.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0030 is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 1 warnings.
Creating bit map...
Saving bit stream in "segment_scan_clock_24.bit".
Bitstream generation is complete.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SEGMENT_SCAN_CLOCK_24.VHD
Scanning    CLOCK_PACK.vhd
Scanning    SEGMENT_SCAN_CLOCK_24.VHD
Writing SEGMENT_SCAN_CLOCK_24.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    CLK_SET.VHD
Scanning    CLOCK_PACK.vhd
Scanning    CLK_SET.VHD
Writing CLK_SET.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_00_23.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_00_23.VHD
Writing COUNT_00_23.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_00_59.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_00_59.VHD
Writing COUNT_00_59.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_0_5.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_0_5.VHD
Writing COUNT_0_5.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_0_9.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_0_9.VHD
Writing COUNT_0_9.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    DECODER.vhd
Scanning    CLOCK_PACK.vhd
Scanning    DECODER.vhd
Writing DECODER.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    DECODER.vhd
Scanning    CLOCK_PACK.vhd
Scanning    DECODER.vhd
Writing DECODER.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    SEGMENT_SCAN_CLOCK_24.VHD
Scanning    CLOCK_PACK.vhd
Scanning    SEGMENT_SCAN_CLOCK_24.VHD
Writing SEGMENT_SCAN_CLOCK_24.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    COUNT_00_23.VHD
Scanning    CLOCK_PACK.vhd
Scanning    COUNT_00_23.VHD
Writing COUNT_00_23.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    DECODER.vhd
Scanning    CLOCK_PACK.vhd
Scanning    DECODER.vhd
Writing DECODER.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/CLOCK_PACK.vhd in Library work.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD in Library work.
Entity <count_0_9> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD in Library work.
Entity <count_0_5> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/CLK_SET.VHD in Library work.
Entity <clk_set> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_00_59.VHD in Library work.
Entity <count_00_59> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_00_23.VHD in Library work.
Entity <count_00_23> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/DECODER.vhd in Library work.
Entity <decoder> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/SEGMENT_SCAN_CLOCK_24.VHD in Library work.
Entity <segment_scan_clock_24> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <segment_scan_clock_24> (Architecture <behavioral>).
Entity <segment_scan_clock_24> analyzed. Unit <segment_scan_clock_24> generated.

Analyzing Entity <clk_set> (Architecture <behavioral>).
Entity <clk_set> analyzed. Unit <clk_set> generated.

Analyzing Entity <count_00_59> (Architecture <behavioral>).
Entity <count_00_59> analyzed. Unit <count_00_59> generated.

Analyzing Entity <count_00_23> (Architecture <behavioral>).
Entity <count_00_23> analyzed. Unit <count_00_23> generated.

Analyzing Entity <decoder> (Architecture <behavioral>).
Entity <decoder> analyzed. Unit <decoder> generated.

Analyzing Entity <count_0_9> (Architecture <behavioral>).
Entity <count_0_9> analyzed. Unit <count_0_9> generated.

Analyzing Entity <count_0_5> (Architecture <behavioral>).
Entity <count_0_5> analyzed. Unit <count_0_5> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count_0_5>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_5.VHD.
    Found 4-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
Unit <count_0_5> synthesized.


Synthesizing Unit <count_0_9>.
    Related source file is C:/HARDWARE/SEGMENT_SCAN_CLOCK_24/COUNT_0_9.VHD.
    Found 4-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
Unit <count_0_9> synthesized.