mono_sim.v

来自「各种基本单元的verilog模块.对初学者很有帮助的.」· Verilog 代码 · 共 54 行

/*********************************************************/
// MODULE:		monostable multivibrator simulation
//
// FILE NAME:	mono_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a monostable multivibrator.
//
/*********************************************************/

// DEFINES

// TOP MODULE
module mono_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg  	trigger;
wire	out;

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the monostable multivibrator
mono mono1(
		.retrig(trigger),
		.q(out));

// Initialize inputs

// Simulate
initial begin
	trigger = 0;
	#10  trigger = ~trigger;
	#200 trigger = ~trigger;
	#300 trigger = ~trigger;
	#100 trigger = ~trigger;
	$finish;
end
endmodule		// mono_sim