norace.v

来自「各种基本单元的verilog模块.对初学者很有帮助的.」· Verilog 代码 · 共 26 行

always @(posedge clk) begin
	case (state)
		`STATE0: begin
			if (sig2) begin
				if (~sig1)
					state <= `STATE1;
				else
					state <= `STATE2;
			end
			else
				state <= `STATE0;
		end
		`STATE1: begin
			if (~sig2)
				state <= `STATE0;
		end
		`STATE2: begin
			if (~sig2)
				state <= `STATE0;
		end
		default: begin
			state <= `STATE0;
		end
	endcase
end