opt.v

来自「各种基本单元的verilog模块.对初学者很有帮助的.」· Verilog 代码 · 共 58 行

/*********************************************************/
// MODULE:		Optimization
//
// FILE NAME:	opt.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Behavioral and RTL
//
// DESCRIPTION:	This module shows the results of optimizing
// logic.
//
/*********************************************************/

// DEFINES

// TOP MODULE
module Opt(
		select,
		in0,
		in1,
		out);

// INPUTS
input 			select;		// Select input
input 			in0;		// Input
input 			in1;		// Input

// OUTPUTS
output 			out;		// Output

// INOUTS

// SIGNAL DECLARATIONS
wire 			select;
wire 			in0;
wire 			in1;
wire			sel0;
wire			sel1;
wire			en0;
wire			en1;
tri 			out;

// PARAMETERS

// ASSIGN STATEMENTS
assign sel1 = select ? 1 : 0;
assign sel0 = select ? 0 : 1;
assign en1 = sel1 & ~sel0;
assign en0 = ~sel1 & sel0;

// MAIN CODE
bufif0 buffer0(out, in0, en0);
bufif0 buffer1(out, in1, en1);

endmodule		// Opt