cnt_beh.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		up/down counter
//
// FILE NAME:	cnt_beh.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Behavioral Level
//
// DESCRIPTION:	This module defines an up/down counter with
// asynchronous set and reset inputs, and synchronous load,
// up/down control, and count enable
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.
`define BITS 8		// Number of bits in counter

// TOP MODULE
module	Counter(
		clk,
		in,
		reset_n,
		preset_n,
		load,
		up_down,
		count_en,
		out,
		carry_out);

// INPUTS
input				clk;		// Clock
input [`BITS-1:0]	in;			// Input
input				reset_n;	// Active low,
								// asynchronous reset
input				preset_n;	// Active low,
								// asynchronous preset
input				load;		// Synchronous load input
input				up_down;	// Synchronous up/down control
input				count_en;	// Synchronous count
								// enable control

// OUTPUTS
output [`BITS-1:0]	out;		// Output
output				carry_out;	// Carry output

// INOUTS

// SIGNAL DECLARATIONS
wire				clk;
wire [`BITS-1:0]	in;
wire				reset_n;
wire				preset_n;
wire				load;
wire				up_down;
wire				count_en;
reg  [`BITS-1:0]  	out;
wire				carry_out;

// PARAMETERS

// ASSIGN STATEMENTS
// When counting up, the carry output is asserted when all
// outputs are 1. When counting down, it is asserted when all
// outputs are 0.
assign #`DEL carry_out = up_down ? &out : ~(|out);

// MAIN CODE

// Look at the edges of reset
always @(posedge reset_n or negedge reset_n) begin
	if (~reset_n)
		#`DEL assign out = `BITS'h0;
	else
		#`DEL deassign out;
end

// Look at the edges of preset
always @(posedge preset_n or negedge preset_n) begin
	if (~preset_n)
		#`DEL assign out = ~`BITS'h0;
	else
		#`DEL deassign out;
end

// Look at the rising edge of clock for state transitions
always @(posedge clk) begin
	if (load) begin
		// In this implementation, load has priority over
		// count enable
		out <= #`DEL in;
	end
	else if (count_en) begin
		if (up_down)
			out <= #`DEL out + `BITS'b1;
		else
			out <= #`DEL out - `BITS'b1;
	end
end
endmodule		// Counter