pkg_full_adder.vhd

来自「全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
package pkg_Full_Adder is

component Full_Adder
  port(
       in1     : in std_logic;
       in2     : in std_logic;
       carryin : in std_logic;
       
       sum     : out std_logic;
       carryout: out std_logic
  );
end component;

end pkg_Full_Adder;