tb_full_adder.vhd

来自「全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼」· VHDL 代码 · 共 46 行

-- tb_Full_Adder.vhd (Test Bench)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pkg_Full_Adder.all;

entity tb_Full_Adder is
end tb_Full_Adder;

architecture arc of tb_Full_Adder is
    signal in1, in2, carryin : std_logic;
    signal sum, carryout     : std_logic;
begin
    process
    begin
        -- 0 ns
        in1 <= '0';  in2 <= '0';  carryin <= '0';  wait for 20 ns;

        -- 20 ns
        in1 <= '0';  in2 <= '0';  carryin <= '1';  wait for 20 ns;

        -- 40 ns???????
        in1 <= '0';  in2 <= '1';  carryin <= '0';  wait for 20 ns;

        in1 <= '0';  in2 <= '1';  carryin <= '1';  wait for 20 ns;
        in1 <= '1';  in2 <= '0';  carryin <= '0';  wait for 20 ns;
        in1 <= '1';  in2 <= '0';  carryin <= '1';  wait for 20 ns;
        in1 <= '1';  in2 <= '1';  carryin <= '0';  wait for 20 ns;
        -- 140 ns 
        in1 <= '1';  in2 <= '1';  carryin <= '1';  wait for 20 ns;
 
        -- 160 ns 
        assert   false
        report   "  xxxxxxx  End of Simulation"
        severity Failure;
     end process;

     Full_Adder_Inst: Full_Adder port map
         ( in1       =>  in1,
           in2       =>  in2,
           carryin   =>  carryin,
           sum       =>  sum,
           carryout  =>  carryout
         );
end arc;