full_adder.vhd

来自「全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼」· VHDL 代码 · 共 26 行

-- Full_Adder.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use work.pkg_Full_Adder.all;

entity Full_Adder is
  port( in1      : in  std_logic;
        in2      : in  std_logic;
        carryin  : in  std_logic;
        
        sum      : out std_logic;
        carryout : out std_logic
      );
end Full_Adder;
architecture arc of Full_Adder is
begin
Do_Full_Adder:
    process( in1, in2, carryin )
        variable result : std_logic_vector( 1 downto 0);
    begin
        result := ('0' & in1) + in2 + carryin;
        carryout <= result(1);
        sum      <= result(0);
    end process Do_Full_Adder;
end arc;