decqpsk.v

来自「QPSK的VERLOG源码」· Verilog 代码 · 共 70 行

/****************************************************/
//MODULE :decQPSK
/***************************************************/
module decQPSK(clk,reset,bita,bitb,bit_out);
input clk;
input reset;
input bita;
input bitb;
output bit_out;

reg bit_out;
reg bita1;
reg bitb1;
reg bita2;
reg bitb2;
reg flag;
reg outa;
reg outb;


always@(posedge clk)
begin
if(reset)
  begin 
  flag=0;
  bita1=0;
  bitb1=0;
  bita2=0;
  bitb2=0;
  outa=0;
  outb=0;
  end
  
 else
  begin
     if(flag==0)    
         begin
               bita1=bita2;
               bita2=bita;
               bitb1=bitb2;
               bitb2=bitb;
   
            if(bita1^bitb1)
                 begin
                   outa=bitb2^bitb1;
                   outb=bita2^bita1;
                 end
           else
                 begin
                   outa=bita2^bita1;
                   outb=bitb2^bitb1;
                 end
        bit_out=outa;
        flag=flag+1;        
                  
         end
     else
     begin
       bit_out=outb;
       flag=flag+1;
     end  
        
       
  
  end
     
    
end

endmodule