test_qpsk.v

来自「QPSK的VERLOG源码」· Verilog 代码 · 共 42 行

/***********************************************/
//MUDULE :test_QPSK
//encode
/***********************************************/
`timescale 1ns/1ns
module test_QPSK;
reg clk;
reg reset;
reg bit_in;
wire bit_out1;
wire bit_out2;

always #10 clk=~clk;
initial
begin
 clk=0;reset=1;bit_in=0;
 #20 reset=0; bit_in=1;
 #20 bit_in=0;
  #20 bit_in=1;
   #40 bit_in=0;
    #20 bit_in=1;
     #60 bit_in=0;
      #20 bit_in=1;
       #20 bit_in=0;
        #40 bit_in=1;
         #40 bit_in=0;
          #20 bit_in=1;
           #60 bit_in=0;
            #20 bit_in=1;
             #40 bit_in=0;
              #20 bit_in=1;
               #40 bit_in=0;
                #20 bit_in=1;
                #10 $stop;





end
QPSKenckde qpsken(clk,reset,bit_in,bit_out1,bit_out2);
endmodule