hamin.v

来自「汉明码的编结码模块」· Verilog 代码 · 共 24 行

/*******************************************/
//MODUlE?hamgen
//????????8??????????
/************************************************/
//DEFINES
`define DELAY 0  //????????
//????
module hamgen(data_in,ham_out);
//????
input [7:0] data_in;//???
output [3:0] ham_out;//?????

//????
wire [7:0] data_in;
wire [3:0] ham_out;

//??
assign #`DELAY  ham_out[3]=data_in[7]^data_in[6]^data_in[4]^data_in[3]^data_in[1];
assign #`DELAY  ham_out[2]=data_in[7]^data_in[5]^data_in[4]^data_in[2]^data_in[1];
assign #`DELAY  ham_out[1]=data_in[6]^data_in[5]^data_in[4]^data_in[0];
assign #`DELAY  ham_out[0]=data_in[3]^data_in[2]^data_in[1]^data_in[0];
endmodule