hamdec.v

汉明码的编结码模块

/*************************************************************/
//MODULE:hamdec
//????????8??????????

/**************************************************************/
//DEFINES
`define DELAY 1
//????
module hamdec(data_in,ham_in,data_out,error);
//????
input[7:0] data_in;//????
input[3:0] ham_in;//????????

output [7:0] data_out;
output error;
 
//????
wire [7:0] data_in;
wire [3:0] ham_in;
reg [7:0] data_out;
reg error;

wire [3:0] temp;

//??
assign #`DELAY temp[0]=ham_in[3]^data_in[7]^data_in[6]^data_in[4]^data_in[3]^data_in[1];
assign #`DELAY temp[1]=ham_in[2]^data_in[7]^data_in[5]^data_in[4]^data_in[2]^data_in[1];
assign #`DELAY temp[2]=ham_in[1]^data_in[6]^data_in[5]^data_in[4]^data_in[0];
assign #`DELAY temp[3]=ham_in[0]^data_in[3]^data_in[2]^data_in[1]^data_in[0];
//??????????????????????????????0?????1

always@(temp or data_in)
begin
           data_out=data_in;
       case(temp)
          4'h0: begin    error=0; end
          4'h1: begin    error=1; end
          4'h2: begin    error=1;  end
          4'h4: begin    error=1; end
          4'h8: begin    error=1; end

          4'h3:begin    data_out[7]=~data_in[7];error=1; end
          4'h5:begin    data_out[6]=~data_in[6];error=1; end
          4'h6:begin    data_out[5]=~data_in[5];error=1; end
          4'h7:begin    data_out[4]=~data_in[4];error=1; end

         4'h9:begin    data_out[3]=~data_in[3];error=1; end
         4'ha:begin    data_out[2]=~data_in[2];error=1; end
         4'hb:begin    data_out[1]=~data_in[1];error=1; end
         4'hc:begin    data_out[0]=~data_in[0];error=1; end
     endcase
end
endmodule