test_decode.v

来自「汉明码的编结码模块」· Verilog 代码 · 共 33 行

/*************************************************************/
//MODULE:hamdec
//????????8??????????

/**************************************************************/
`timescale 1ns/1ns
module test_decode;

reg [7:0] data_in;
reg [3:0] ham_in;
 wire [7:0] data_out;
 wire error;
 
 initial
 begin
 data_in=0;
 ham_in=0;
 # 10  data_in=1; ham_in=2;
 # 10  data_in=2; ham_in=3;
 # 10  data_in=3; ham_in=4;
 # 10  data_in=4; ham_in=5;
 # 10  data_in=5; ham_in=6;
 # 10  data_in=6; ham_in=7;
 # 10  data_in=7; ham_in=0;
 # 10  data_in=8; ham_in=1;
 # 10  data_in=9; ham_in=2;
 # 10  data_in=10; ham_in=3;
 # 10 $stop;
 
 end
 hamdec  Hamdec(data_in,ham_in,data_out,error);

 endmodule