test_encode.v

来自「汉明码的编结码模块」· Verilog 代码 · 共 35 行

/*******************************************/
//MODUlE?hamgen
//????????8??????????
//mingzhaoyan@isee      2006.3.19
/************************************************/

`timescale	1ns/1ns
module  test_encode;

reg	[7:0]	signal;
wire    [3:0]		signal_encoded;

initial
begin
	signal=0;
#10	signal=1;
#10	signal=2;
#10	signal=3;
#10	signal=4;
#10	signal=5;
#10	signal=6;
#10	signal=7;
#10	signal=8;
#10	signal=9;
#10	signal=10;
#10	$stop;

end


hamgen  HAMGEN(.data_in(signal),
               .ham_out(signal_encoded));

endmodule