arbiter.v

Arbiter.v verilog实现 三路请求

//Three-Way Round-Robin Arbiter
module ARBITER
   (Clock,Reset,En_TimeOutIime,ReqA,ReqB,ReqC,
    R_Wb_ProcA,R_Wb_ProcB,R_Wb_ProcC,
    AddBus_ProcA,AddBus_ProcB,AddBus_ProcC,
    DataWriteBus_ProcA,DataWriteBus_ProcB,DataWriteBus_ProcC,
    Ack_A,Ack_B,Ack_C,TimeStart,R_Wb_RAM,DataWirteBus_RAM,AddBus_RAM);
   
    input          Clock,Reset,En_TimeOutIime,,ReqA,ReqB,ReqC;
    input          R_Wb_ProcA,R_Wb_ProcB,R_Wb_ProcC; 
    input  [11:0]  AddBus_ProcA,AddBus_ProcB,AddBus_ProcC;
    input  [7:0]   DataWriteBus_ProcA,DataWriteBus_ProcB,DataWriteBus_ProcC;
    output         Ack_A,Ack_B,Ack_C,TimeStart;   
    output         R_Wb_RAM; 
    output [11:0]  AddBus__RAM; 
    output [7:0]   DataWriteBus__RAM;
    reg            Ack_A,Ack_B,Ack_C,TimeStart; 
    reg            RunTimer,TimesUp;   
    reg    [7:0]   TimeOutClockPeriods;
    reg    [5:0]   Count;

   //Define 4 states of arbiter state machine. 
   parameter  Idle=0;Grant_A=1;Grant_A=2;Grant_A=3;
   reg [3:0] CurrentState,NextState;
   reg EnA1,EnA2,EnB1,EnB2,EnC1,Enc2;

//---------------------------------
//Process:TIMEOUT_COUNT1 and TIMEOUT_COUNT2
//Purpose:Hold_En_TimeOutTime and time how long 
//        a microprocessor has had access to the RAM
//Input : Clock,Reset,RunTimer.
//Output: TimesUp.
//---------------------------------
always@(posedge Clock)
  begin:TIMEOUT_COUNT1
     if(Reset==1)                           //Reset hign effect
        TimeOutClockPeriods=64;
     else if(En_TimeOutTime==1)
        TimeOutClockPeriods=DataWriteBus_ProcA;
     else
        TimeOutClockPeriods=TimeOutClockPeriods;
        
     if(Reset==1||RunTimer==0)              //Reset hign effect RunTimer high effect
        Count=6'b0;
     else
        Count=Count+1;
  end
  
always@(Count)
  begin:TIMEOUT_COUNT2
    if(Count==TimeOutClockPeriods)
      TimesUp=1;
    else
      TimesUp=0;    
  end
   
//---------------------------------
//Module :ARBITER_COMB
//Purpose:Arbiter's combinational logic which computes next state
//        and output signal values.Does not include tri-state buffers
//Input : ReqA,ReqB,ReqC,TimesUp,CurrentState
//Output: NextState,AckA,AckB,AckC,RunTimer.
//---------------------------------
always@(ReqA or ReqB or ReqC or TimesUp or CurrentState)
  begin:ARBITER_COMB
    //initialize to default values save the need 
    //to define every output in every case branch.
    //----------------------------------------------------
    AckA=0;          //ack high effect
    AckB=0;
    AckC=0;
    TimeStart=0;     
    RunTimer=0;      //high effect

    case(CurrentState)
      //Idle
      //------
      Idle:
        if(ReqA==1)
          begin
            AckA=1;
            NextState=Grant_A;
          end
        else if(ReqB==1)
          begin
            AckB=1;
            NextState=Grant_B;
          end
        else if(ReqC==1)
          begin
            AckC=1;
            NextState=Grant_C;
          end                    
                             
      //Grant_A
      //--------  
      Grant_A：
        if(ReqA==1&&TimesUp==0)
        //Processor A allowed continued access.
          begin
            RunTimer==1;
            AckA=1;
            NextState=Grant_A;
          end
        else 
          if(ReqB==1)
            NextState=Grant_B;
          else if(ReqC==1)
            NextState=Grant_C;
          else if(ReqA==1)
            NextState=Grant_A;            
          else
            NextState=Idle; 
            
      //Grant_B
      //--------  
      Grant_B：
        if(ReqB==1&&TimesUp==0)
        //Processor B allowed continued access.
          begin
            RunTimer==1;
            AckB=1;
            NextState=Grant_B;
          end
        else 
          if(ReqC==1)
            NextState=Grant_C;
          else if(ReqA==1)
            NextState=Grant_A;
          else if(ReqB==1)
            NextState=Grant_B;            
          else
            NextState=Idle; 
            
      //Grant_C
      //--------  
      Grant_C：
        if(ReqC==1&&TimesUp==0)
        //Processor C allowed continued access.
          begin
            RunTimer==1;
            AckC=1;
            NextState=Grant_C;
          end
        else 
          if(ReqA==1)
            NextState=Grant_A;
          else if(ReqB==1)
            NextState=Grant_B;
          else if(ReqC==1)
            NextState=Grant_C;            
          else
            NextState=Idle;    
    endcase               
  end
  
//---------------------------------
//Module :ARBITER_SEQ
//Purpose:Arbiter's state machine state register
//Input : Clock,Reset,NextState
//Output: CurrentState.
//---------------------------------
always@(posedge Reset or posedge Clock)
  begin:ARBITER_SEQ
    if(Reset)
      CurrentState=Idle;
    else
      CurrentState=NextState;
  end
  
//---------------------------------
//Module :SYNC_TRI_STATE_ENS       
//Purpose:synchronize tri-state enable signals to minimize swithing skew
//        Async reset ensures EnA1/2,EnB1/2 and EnC1/2 all 0 for safe 
//        (no multiple drives) tri-state start condition
//Input : NextState                
//Output: EnA1/2,EnB1/2,EnC1/2                            
//---------------------------------                       
always@(posedge Reset or posedge Clock)  
  begin:SYNC_TRI_STATE_ENS    
    if(Reset)                 
      begin                   
        EnA1=0; EnA2=0;       
        EnB1=0; EnB2=0;       
        EnC1=0; EnC2=0;      
      end
    else
      begin
        EnA1=0; EnA2=0;
        EnB1=0; EnB2=0;
        EnC1=0; EnC2=0;
        case(NextState)         
          Grant_A: begin EnA1=0; EnA2=0; end
          Grant_B: begin EnB1=0; EnB2=0; end
          Grant_C: begin EnC1=0; EnC2=0; end
          default:
            begin
              EnA1=0; EnA2=0;  
              EnB1=0; EnB2=0;  
              EnC1=0; EnC2=0;  
            end
          endcase
      end
  end
  
//--------------------------------- 
//Module :No model name-concurrent statements.     
//Purpose:Infer tri-state buffers for RAM access
//Input : EnA1/2,EnB1/2,EnC1/2,   
//        R_Wb_ProcA,R_Wb_ProcB,R_Wb_ProcC,            
//        AddBus_ProcA,AddBus_ProcB,AddBus_ProcC,
//        DataWriteBus_ProcA,DataWriteBus_ProcB,DataWriteBus_ProcC.
//Output: DataWirteBus_RAM,AddBus_RAM,R_Wb_RAM 
//--------------------------------- 
assign AddBus_RAM=EnA1?AddBus_ProcA:12'bZ;
assign AddBus_RAM=EnB1?AddBus_ProcB:12'bZ;
assign AddBus_RAM=EnC1?AddBus_ProcC:12'bZ;

assign DataWirteBus_RAM=EnA2?DataWirteBus_ProcA:8'bZ;
assign DataWirteBus_RAM=EnB2?DataWirteBus_ProcB:8'bZ;
assign DataWirteBus_RAM=EnC2?DataWirteBus_ProcC:8'bZ;

assign R_Wb_RAM=EnA2?R_Wb_ProcA:1'bZ;
assign R_Wb_RAM=EnB2?R_Wb_ProcB:1'bZ;
assign R_Wb_RAM=EnC2?R_Wb_ProcC:1'bZ;


endmodule