counter_7seg.map.rpt

带分频器的bcd计数电路设计

+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 26    ;
; Number of synthesis-generated cells                    ; 61    ;
; Number of WYSIWYG LUTs                                 ; 26    ;
; Number of synthesis-generated LUTs                     ; 43    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 35    ;
; Number of cells with combinational logic only          ; 52    ;
; Number of cells with registers only                    ; 18    ;
; Number of cells with combinational logic and registers ; 17    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 35    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 9     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
counter_7seg
 |-- f50MHz_to_1Hz:inst
 |-- bcd_counter:inst4
 |-- decoder_7seg_new:inst5
 |-- decoder_7seg_new:inst6


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                          ;
+-----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------+
; Compilation Hierarchy Node  ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                  ;
+-----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------+
; |counter_7seg               ; 87 (0)      ; 35           ; 0           ; 0            ; 0       ; 0         ; 0         ; 17   ; 0            ; 52 (0)       ; 18 (0)            ; 17 (0)           ; 26 (0)          ; |counter_7seg                        ;
;    |bcd_counter:inst4|      ; 13 (13)     ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 4 (4)        ; 4 (4)             ; 5 (5)            ; 0 (0)           ; |counter_7seg|bcd_counter:inst4      ;
;    |decoder_7seg_new:inst5| ; 7 (7)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |counter_7seg|decoder_7seg_new:inst5 ;
;    |decoder_7seg_new:inst6| ; 7 (7)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |counter_7seg|decoder_7seg_new:inst6 ;
;    |f50MHz_to_1Hz:inst|     ; 60 (60)     ; 26           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 34 (34)      ; 14 (14)           ; 12 (12)          ; 26 (26)         ; |counter_7seg|f50MHz_to_1Hz:inst     ;
+-----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Quartus/counter_7seg/counter_7seg.map.eqn.


+-------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                          ;
+----------------------------------+-----------------+--------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path               ;
+----------------------------------+-----------------+--------------------------------------------+
; f50MHz_to_1Hz.v                  ; yes             ; E:/Quartus/counter_7seg/f50MHz_to_1Hz.v    ;
; decoder_7seg_new.v               ; yes             ; E:/Quartus/counter_7seg/decoder_7seg_new.v ;
; counter_7seg.bdf                 ; yes             ; E:/Quartus/counter_7seg/counter_7seg.bdf   ;
; bcd_counter.v                    ; yes             ; E:/Quartus/counter_7seg/bcd_counter.v      ;
+----------------------------------+-----------------+--------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 87      ;
; Total combinational functions     ; 69      ;
; Total 4-input functions           ; 28      ;
; Total 3-input functions           ; 2       ;
; Total 2-input functions           ; 13      ;
; Total 1-input functions           ; 26      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 35      ;
; Total logic cells in carry chains ; 26      ;
; I/O pins                          ; 17      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 16      ;
; Total fan-out                     ; 276     ;
; Average fan-out                   ; 2.65    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
    Info: Processing started: Mon Mar 27 11:51:13 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off counter_7seg -c counter_7seg
Info: Found 1 design units, including 1 entities, in source file f50MHz_to_1Hz.v
    Info: Found entity 1: f50MHz_to_1Hz
Info: Found 1 design units, including 1 entities, in source file decoder_7seg_new.v
    Info: Found entity 1: decoder_7seg_new
Info: Found 1 design units, including 1 entities, in source file counter_7seg.bdf
    Info: Found entity 1: counter_7seg
Info: Found 1 design units, including 1 entities, in source file bcd_counter.v
    Info: Found entity 1: bcd_counter
Warning: Verilog HDL assignment warning at bcd_counter.v(26): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at bcd_counter.v(30): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at f50MHz_to_1Hz.v(15): truncated value with size 17 to match size of target (16)
Warning: Verilog HDL assignment warning at f50MHz_to_1Hz.v(23): truncated value with size 11 to match size of target (10)
Info: Duplicate registers merged to single register
    Info: Duplicate register "f50MHz_to_1Hz:inst|count1[15]" merged to single register "f50MHz_to_1Hz:inst|clk_1khz~reg0"
    Info: Duplicate register "f50MHz_to_1Hz:inst|clk_1hz" merged to single register "f50MHz_to_1Hz:inst|count2[9]"
Info: Implemented 104 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 15 output pins
    Info: Implemented 87 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Mon Mar 27 11:51:14 2006
    Info: Elapsed time: 00:00:01