counter_7seg.map.qmsg

带分频器的bcd计数电路设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition " "Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 27 11:51:13 2006 " "Info: Processing started: Mon Mar 27 11:51:13 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off counter_7seg -c counter_7seg " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off counter_7seg -c counter_7seg" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f50MHz_to_1Hz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file f50MHz_to_1Hz.v" { { "Info" "ISGN_ENTITY_NAME" "1 f50MHz_to_1Hz " "Info: Found entity 1: f50MHz_to_1Hz" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder_7seg_new.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file decoder_7seg_new.v" { { "Info" "ISGN_ENTITY_NAME" "1 decoder_7seg_new " "Info: Found entity 1: decoder_7seg_new" {  } { { "decoder_7seg_new.v" "" { Text "E:/Quartus/counter_7seg/decoder_7seg_new.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter_7seg.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter_7seg.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 counter_7seg " "Info: Found entity 1: counter_7seg" {  } { { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd_counter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bcd_counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd_counter " "Info: Found entity 1: bcd_counter" {  } { { "bcd_counter.v" "" { Text "E:/Quartus/counter_7seg/bcd_counter.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 bcd_counter.v(26) " "Warning: Verilog HDL assignment warning at bcd_counter.v(26): truncated value with size 5 to match size of target (4)" {  } { { "bcd_counter.v" "" { Text "E:/Quartus/counter_7seg/bcd_counter.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 bcd_counter.v(30) " "Warning: Verilog HDL assignment warning at bcd_counter.v(30): truncated value with size 5 to match size of target (4)" {  } { { "bcd_counter.v" "" { Text "E:/Quartus/counter_7seg/bcd_counter.v" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "17 16 f50MHz_to_1Hz.v(15) " "Warning: Verilog HDL assignment warning at f50MHz_to_1Hz.v(15): truncated value with size 17 to match size of target (16)" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "11 10 f50MHz_to_1Hz.v(23) " "Warning: Verilog HDL assignment warning at f50MHz_to_1Hz.v(23): truncated value with size 11 to match size of target (10)" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 23 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "f50MHz_to_1Hz:inst\|count1\[15\] f50MHz_to_1Hz:inst\|clk_1khz~reg0 " "Info: Duplicate register \"f50MHz_to_1Hz:inst\|count1\[15\]\" merged to single register \"f50MHz_to_1Hz:inst\|clk_1khz~reg0\"" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "f50MHz_to_1Hz:inst\|clk_1hz f50MHz_to_1Hz:inst\|count2\[9\] " "Info: Duplicate register \"f50MHz_to_1Hz:inst\|clk_1hz\" merged to single register \"f50MHz_to_1Hz:inst\|count2\[9\]\"" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 2 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "104 " "Info: Implemented 104 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "87 " "Info: Implemented 87 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 27 11:51:14 2006 " "Info: Processing ended: Mon Mar 27 11:51:14 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}