counter_7seg.fit.qmsg

带分频器的bcd计数电路设计

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 0 1 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 0 48 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 15 37 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 15 total pin(s) used --  37 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 54 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  54 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 0 48 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 1 47 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  47 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 55 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  55 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 52 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 4 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 4 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.335 ns register register " "Info: Estimated most critical path is register to register delay of 3.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f50MHz_to_1Hz:inst\|count1\[3\] 1 REG LAB_X21_Y21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y21; Fanout = 4; REG Node = 'f50MHz_to_1Hz:inst\|count1\[3\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { f50MHz_to_1Hz:inst|count1[3] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.451 ns) 1.471 ns f50MHz_to_1Hz:inst\|add~275COUTCOUT1_299 2 COMB LAB_X22_Y22 2 " "Info: 2: + IC(1.020 ns) + CELL(0.451 ns) = 1.471 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'f50MHz_to_1Hz:inst\|add~275COUTCOUT1_299'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "1.471 ns" { f50MHz_to_1Hz:inst|count1[3] f50MHz_to_1Hz:inst|add~275COUTCOUT1_299 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.533 ns f50MHz_to_1Hz:inst\|add~276COUTCOUT1_300 3 COMB LAB_X22_Y22 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.533 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'f50MHz_to_1Hz:inst\|add~276COUTCOUT1_300'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "0.062 ns" { f50MHz_to_1Hz:inst|add~275COUTCOUT1_299 f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.595 ns f50MHz_to_1Hz:inst\|add~277COUTCOUT1_301 4 COMB LAB_X22_Y22 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.595 ns; Loc. = LAB_X22_Y22; Fanout = 2; COMB Node = 'f50MHz_to_1Hz:inst\|add~277COUTCOUT1_301'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "0.062 ns" { f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 2.044 ns f50MHz_to_1Hz:inst\|add~278 5 COMB LAB_X22_Y22 1 " "Info: 5: + IC(0.000 ns) + CELL(0.449 ns) = 2.044 ns; Loc. = LAB_X22_Y22; Fanout = 1; COMB Node = 'f50MHz_to_1Hz:inst\|add~278'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "0.449 ns" { f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.583 ns) 3.335 ns f50MHz_to_1Hz:inst\|count1\[6\] 6 REG LAB_X21_Y21 4 " "Info: 6: + IC(0.708 ns) + CELL(0.583 ns) = 3.335 ns; Loc. = LAB_X21_Y21; Fanout = 4; REG Node = 'f50MHz_to_1Hz:inst\|count1\[6\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "1.291 ns" { f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.607 ns 48.19 % " "Info: Total cell delay = 1.607 ns ( 48.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.728 ns 51.81 % " "Info: Total interconnect delay = 1.728 ns ( 51.81 % )" {  } {  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.335 ns" { f50MHz_to_1Hz:inst|count1[3] f50MHz_to_1Hz:inst|add~275COUTCOUT1_299 f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 27 12:05:37 2006 " "Info: Processing ended: Mon Mar 27 12:05:37 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}