counter_7seg.fit.qmsg

带分频器的bcd计数电路设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition " "Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 27 12:05:28 2006 " "Info: Processing started: Mon Mar 27 12:05:28 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=on --export_settings_files=off counter_7seg -c counter_7seg " "Info: Command: quartus_fit --import_settings_files=on --export_settings_files=off counter_7seg -c counter_7seg" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "counter_7seg EP1S10F780C6 " "Info: Selected device EP1S10F780C6 for design \"counter_7seg\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F780I6 " "Info: Device EP1S10F780I6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F780C6ES " "Info: Device EP1S10F780C6ES is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 17 " "Info: No exact pin location assignment(s) for 1 pins of 17 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "cn " "Info: Pin cn not assigned to an exact location on the device" {  } { { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 320 472 648 336 "cn" "" } } } } { "d:/altera/quartus42sp1/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42sp1/bin/Assignment Editor.qase" 1 { { 0 "cn" } } } } { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { cn } "NODE_NAME" } "" } } { "E:/Quartus/counter_7seg/counter_7seg.fld" "" { Floorplan "E:/Quartus/counter_7seg/counter_7seg.fld" "" "" { cn } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN K17 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN K17" {  } { { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 144 -104 64 160 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "f50MHz_to_1Hz:inst\|clk_1khz~reg0 Global clock " "Info: Automatically promoted some destinations of signal \"f50MHz_to_1Hz:inst\|clk_1khz~reg0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "f50MHz_to_1Hz:inst\|add~287 " "Info: Destination \"f50MHz_to_1Hz:inst\|add~287\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "f50MHz_to_1Hz:inst\|reduce_nor~169 " "Info: Destination \"f50MHz_to_1Hz:inst\|reduce_nor~169\" may be non-global or may not use global clock" {  } {  } 0}  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "f50MHz_to_1Hz:inst\|count2\[9\] Global clock " "Info: Automatically promoted some destinations of signal \"f50MHz_to_1Hz:inst\|count2\[9\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "f50MHz_to_1Hz:inst\|add~271 " "Info: Destination \"f50MHz_to_1Hz:inst\|add~271\" may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "f50MHz_to_1Hz:inst\|reduce_nor~166 " "Info: Destination \"f50MHz_to_1Hz:inst\|reduce_nor~166\" may be non-global or may not use global clock" {  } {  } 0}  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 25 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clr Global clock " "Info: Automatically promoted signal \"clr\" to use Global clock" {  } { { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 264 56 224 280 "clr" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clr " "Info: Pin \"clr\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 264 56 224 280 "clr" "" } } } } { "d:/altera/quartus42sp1/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42sp1/bin/Assignment Editor.qase" 1 { { 0 "clr" } } } } { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { clr } "NODE_NAME" } "" } } { "E:/Quartus/counter_7seg/counter_7seg.fld" "" { Floorplan "E:/Quartus/counter_7seg/counter_7seg.fld" "" "" { clr } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0}