counter_7seg.tan.qmsg

带分频器的bcd计数电路设计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register f50MHz_to_1Hz:inst\|count1\[4\] register f50MHz_to_1Hz:inst\|count1\[6\] 262.88 MHz 3.804 ns Internal " "Info: Clock \"clk\" has Internal fmax of 262.88 MHz between source register \"f50MHz_to_1Hz:inst\|count1\[4\]\" and destination register \"f50MHz_to_1Hz:inst\|count1\[6\]\" (period= 3.804 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.618 ns + Longest register register " "Info: + Longest register to register delay is 3.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f50MHz_to_1Hz:inst\|count1\[4\] 1 REG LC_X21_Y21_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y21_N7; Fanout = 4; REG Node = 'f50MHz_to_1Hz:inst\|count1\[4\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { f50MHz_to_1Hz:inst|count1[4] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.451 ns) 1.577 ns f50MHz_to_1Hz:inst\|add~276COUTCOUT1_300 2 COMB LC_X22_Y22_N6 2 " "Info: 2: + IC(1.126 ns) + CELL(0.451 ns) = 1.577 ns; Loc. = LC_X22_Y22_N6; Fanout = 2; COMB Node = 'f50MHz_to_1Hz:inst\|add~276COUTCOUT1_300'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "1.577 ns" { f50MHz_to_1Hz:inst|count1[4] f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.639 ns f50MHz_to_1Hz:inst\|add~277COUTCOUT1_301 3 COMB LC_X22_Y22_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.639 ns; Loc. = LC_X22_Y22_N7; Fanout = 2; COMB Node = 'f50MHz_to_1Hz:inst\|add~277COUTCOUT1_301'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "0.062 ns" { f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 2.088 ns f50MHz_to_1Hz:inst\|add~278 4 COMB LC_X22_Y22_N8 1 " "Info: 4: + IC(0.000 ns) + CELL(0.449 ns) = 2.088 ns; Loc. = LC_X22_Y22_N8; Fanout = 1; COMB Node = 'f50MHz_to_1Hz:inst\|add~278'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "0.449 ns" { f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.489 ns) 3.618 ns f50MHz_to_1Hz:inst\|count1\[6\] 5 REG LC_X21_Y21_N8 4 " "Info: 5: + IC(1.041 ns) + CELL(0.489 ns) = 3.618 ns; Loc. = LC_X21_Y21_N8; Fanout = 4; REG Node = 'f50MHz_to_1Hz:inst\|count1\[6\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "1.530 ns" { f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.451 ns 40.11 % " "Info: Total cell delay = 1.451 ns ( 40.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.167 ns 59.89 % " "Info: Total interconnect delay = 2.167 ns ( 59.89 % )" {  } {  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.618 ns" { f50MHz_to_1Hz:inst|count1[4] f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.618 ns" { f50MHz_to_1Hz:inst|count1[4] f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } { 0.000ns 1.126ns 0.000ns 0.000ns 1.041ns } { 0.000ns 0.451ns 0.062ns 0.449ns 0.489ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_K17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_K17; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { clk } "NODE_NAME" } "" } } { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 144 -104 64 160 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.768 ns) + CELL(0.560 ns) 3.348 ns f50MHz_to_1Hz:inst\|count1\[6\] 2 REG LC_X21_Y21_N8 4 " "Info: 2: + IC(1.768 ns) + CELL(0.560 ns) = 3.348 ns; Loc. = LC_X21_Y21_N8; Fanout = 4; REG Node = 'f50MHz_to_1Hz:inst\|count1\[6\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "2.328 ns" { clk f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns 47.19 % " "Info: Total cell delay = 1.580 ns ( 47.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.768 ns 52.81 % " "Info: Total interconnect delay = 1.768 ns ( 52.81 % )" {  } {  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.348 ns" { clk f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~out0 f50MHz_to_1Hz:inst|count1[6] } { 0.000ns 0.000ns 1.768ns } { 0.000ns 1.020ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_K17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_K17; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { clk } "NODE_NAME" } "" } } { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 144 -104 64 160 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.768 ns) + CELL(0.560 ns) 3.348 ns f50MHz_to_1Hz:inst\|count1\[4\] 2 REG LC_X21_Y21_N7 4 " "Info: 2: + IC(1.768 ns) + CELL(0.560 ns) = 3.348 ns; Loc. = LC_X21_Y21_N7; Fanout = 4; REG Node = 'f50MHz_to_1Hz:inst\|count1\[4\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "2.328 ns" { clk f50MHz_to_1Hz:inst|count1[4] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns 47.19 % " "Info: Total cell delay = 1.580 ns ( 47.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.768 ns 52.81 % " "Info: Total interconnect delay = 1.768 ns ( 52.81 % )" {  } {  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.348 ns" { clk f50MHz_to_1Hz:inst|count1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~out0 f50MHz_to_1Hz:inst|count1[4] } { 0.000ns 0.000ns 1.768ns } { 0.000ns 1.020ns 0.560ns } } }  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.348 ns" { clk f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~out0 f50MHz_to_1Hz:inst|count1[6] } { 0.000ns 0.000ns 1.768ns } { 0.000ns 1.020ns 0.560ns } } } { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.348 ns" { clk f50MHz_to_1Hz:inst|count1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~out0 f50MHz_to_1Hz:inst|count1[4] } { 0.000ns 0.000ns 1.768ns } { 0.000ns 1.020ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.618 ns" { f50MHz_to_1Hz:inst|count1[4] f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.618 ns" { f50MHz_to_1Hz:inst|count1[4] f50MHz_to_1Hz:inst|add~276COUTCOUT1_300 f50MHz_to_1Hz:inst|add~277COUTCOUT1_301 f50MHz_to_1Hz:inst|add~278 f50MHz_to_1Hz:inst|count1[6] } { 0.000ns 1.126ns 0.000ns 0.000ns 1.041ns } { 0.000ns 0.451ns 0.062ns 0.449ns 0.489ns } } } { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.348 ns" { clk f50MHz_to_1Hz:inst|count1[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~out0 f50MHz_to_1Hz:inst|count1[6] } { 0.000ns 0.000ns 1.768ns } { 0.000ns 1.020ns 0.560ns } } } { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "3.348 ns" { clk f50MHz_to_1Hz:inst|count1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~out0 f50MHz_to_1Hz:inst|count1[4] } { 0.000ns 0.000ns 1.768ns } { 0.000ns 1.020ns 0.560ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk low\[0\] bcd_counter:inst4\|low\[3\] 18.965 ns register " "Info: tco from clock \"clk\" to destination pin \"low\[0\]\" through register \"bcd_counter:inst4\|low\[3\]\" is 18.965 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.309 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 13.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_K17 16 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_K17; Fanout = 16; CLK Node = 'clk'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { clk } "NODE_NAME" } "" } } { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 144 -104 64 160 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.768 ns) + CELL(0.736 ns) 3.524 ns f50MHz_to_1Hz:inst\|clk_1khz~reg0 2 REG LC_X22_Y21_N8 12 " "Info: 2: + IC(1.768 ns) + CELL(0.736 ns) = 3.524 ns; Loc. = LC_X22_Y21_N8; Fanout = 12; REG Node = 'f50MHz_to_1Hz:inst\|clk_1khz~reg0'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "2.504 ns" { clk f50MHz_to_1Hz:inst|clk_1khz~reg0 } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.223 ns) + CELL(0.736 ns) 8.483 ns f50MHz_to_1Hz:inst\|count2\[9\] 3 REG LC_X13_Y22_N7 11 " "Info: 3: + IC(4.223 ns) + CELL(0.736 ns) = 8.483 ns; Loc. = LC_X13_Y22_N7; Fanout = 11; REG Node = 'f50MHz_to_1Hz:inst\|count2\[9\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "4.959 ns" { f50MHz_to_1Hz:inst|clk_1khz~reg0 f50MHz_to_1Hz:inst|count2[9] } "NODE_NAME" } "" } } { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.266 ns) + CELL(0.560 ns) 13.309 ns bcd_counter:inst4\|low\[3\] 4 REG LC_X13_Y30_N2 10 " "Info: 4: + IC(4.266 ns) + CELL(0.560 ns) = 13.309 ns; Loc. = LC_X13_Y30_N2; Fanout = 10; REG Node = 'bcd_counter:inst4\|low\[3\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "4.826 ns" { f50MHz_to_1Hz:inst|count2[9] bcd_counter:inst4|low[3] } "NODE_NAME" } "" } } { "bcd_counter.v" "" { Text "E:/Quartus/counter_7seg/bcd_counter.v" 2 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.052 ns 22.93 % " "Info: Total cell delay = 3.052 ns ( 22.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.257 ns 77.07 % " "Info: Total interconnect delay = 10.257 ns ( 77.07 % )" {  } {  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "13.309 ns" { clk f50MHz_to_1Hz:inst|clk_1khz~reg0 f50MHz_to_1Hz:inst|count2[9] bcd_counter:inst4|low[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "13.309 ns" { clk clk~out0 f50MHz_to_1Hz:inst|clk_1khz~reg0 f50MHz_to_1Hz:inst|count2[9] bcd_counter:inst4|low[3] } { 0.000ns 0.000ns 1.768ns 4.223ns 4.266ns } { 0.000ns 1.020ns 0.736ns 0.736ns 0.560ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "bcd_counter.v" "" { Text "E:/Quartus/counter_7seg/bcd_counter.v" 2 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.480 ns + Longest register pin " "Info: + Longest register to pin delay is 5.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bcd_counter:inst4\|low\[3\] 1 REG LC_X13_Y30_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y30_N2; Fanout = 10; REG Node = 'bcd_counter:inst4\|low\[3\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "" { bcd_counter:inst4|low[3] } "NODE_NAME" } "" } } { "bcd_counter.v" "" { Text "E:/Quartus/counter_7seg/bcd_counter.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.459 ns) 1.445 ns decoder_7seg_new:inst6\|reduce_or~61 2 COMB LC_X12_Y30_N4 1 " "Info: 2: + IC(0.986 ns) + CELL(0.459 ns) = 1.445 ns; Loc. = LC_X12_Y30_N4; Fanout = 1; COMB Node = 'decoder_7seg_new:inst6\|reduce_or~61'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "1.445 ns" { bcd_counter:inst4|low[3] decoder_7seg_new:inst6|reduce_or~61 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.531 ns) + CELL(2.504 ns) 5.480 ns low\[0\] 3 PIN PIN_C21 0 " "Info: 3: + IC(1.531 ns) + CELL(2.504 ns) = 5.480 ns; Loc. = PIN_C21; Fanout = 0; PIN Node = 'low\[0\]'" {  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "4.035 ns" { decoder_7seg_new:inst6|reduce_or~61 low[0] } "NODE_NAME" } "" } } { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 224 744 920 240 "low\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.963 ns 54.07 % " "Info: Total cell delay = 2.963 ns ( 54.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.517 ns 45.93 % " "Info: Total interconnect delay = 2.517 ns ( 45.93 % )" {  } {  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "5.480 ns" { bcd_counter:inst4|low[3] decoder_7seg_new:inst6|reduce_or~61 low[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "5.480 ns" { bcd_counter:inst4|low[3] decoder_7seg_new:inst6|reduce_or~61 low[0] } { 0.000ns 0.986ns 1.531ns } { 0.000ns 0.459ns 2.504ns } } }  } 0}  } { { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "13.309 ns" { clk f50MHz_to_1Hz:inst|clk_1khz~reg0 f50MHz_to_1Hz:inst|count2[9] bcd_counter:inst4|low[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "13.309 ns" { clk clk~out0 f50MHz_to_1Hz:inst|clk_1khz~reg0 f50MHz_to_1Hz:inst|count2[9] bcd_counter:inst4|low[3] } { 0.000ns 0.000ns 1.768ns 4.223ns 4.266ns } { 0.000ns 1.020ns 0.736ns 0.736ns 0.560ns } } } { "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" "" { Report "E:/Quartus/counter_7seg/db/counter_7seg_cmp.qrpt" Compiler "counter_7seg" "UNKNOWN" "V1" "E:/Quartus/counter_7seg/db/counter_7seg.quartus_db" { Floorplan "E:/Quartus/counter_7seg/" "" "5.480 ns" { bcd_counter:inst4|low[3] decoder_7seg_new:inst6|reduce_or~61 low[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42sp1/bin/Technology_Viewer.qrui" "5.480 ns" { bcd_counter:inst4|low[3] decoder_7seg_new:inst6|reduce_or~61 low[0] } { 0.000ns 0.986ns 1.531ns } { 0.000ns 0.459ns 2.504ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 27 12:05:44 2006 " "Info: Processing ended: Mon Mar 27 12:05:44 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}