counter_7seg.tan.qmsg

带分频器的bcd计数电路设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition " "Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 27 12:05:44 2006 " "Info: Processing started: Mon Mar 27 12:05:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off counter_7seg -c counter_7seg --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter_7seg -c counter_7seg --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "counter_7seg.bdf" "" { Schematic "E:/Quartus/counter_7seg/counter_7seg.bdf" { { 144 -104 64 160 "clk" "" } } } } { "d:/altera/quartus42sp1/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42sp1/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f50MHz_to_1Hz:inst\|clk_1khz~reg0 " "Info: Detected ripple clock \"f50MHz_to_1Hz:inst\|clk_1khz~reg0\" as buffer" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 17 -1 0 } } { "d:/altera/quartus42sp1/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42sp1/bin/Assignment Editor.qase" 1 { { 0 "f50MHz_to_1Hz:inst\|clk_1khz~reg0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "f50MHz_to_1Hz:inst\|count2\[9\] " "Info: Detected ripple clock \"f50MHz_to_1Hz:inst\|count2\[9\]\" as buffer" {  } { { "f50MHz_to_1Hz.v" "" { Text "E:/Quartus/counter_7seg/f50MHz_to_1Hz.v" 25 -1 0 } } { "d:/altera/quartus42sp1/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42sp1/bin/Assignment Editor.qase" 1 { { 0 "f50MHz_to_1Hz:inst\|count2\[9\]" } } } }  } 0}  } {  } 0}