📄 counter_7seg.pin
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-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- Bank 9: 3.3V
-- Bank 10: 3.3V
-- Bank 11: 3.3V
-- Bank 12: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
---------------------------------------------------------------------------------
Quartus II Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Web Edition
CHIP "counter_7seg" ASSIGNED TO AN: EP1S10F780C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCCIO4 : A2 : power : : 3.3V : 4 :
RESERVED_INPUT : A3 : : : : 4 :
RESERVED_INPUT : A4 : : : : 4 :
RESERVED_INPUT : A5 : : : : 4 :
RESERVED_INPUT : A6 : : : : 4 :
RESERVED_INPUT : A7 : : : : 4 :
RESERVED_INPUT : A8 : : : : 4 :
RESERVED_INPUT : A9 : : : : 4 :
RESERVED_INPUT : A10 : : : : 4 :
RESERVED_INPUT : A11 : : : : 4 :
VCCIO4 : A12 : power : : 3.3V : 4 :
NC : A13 : : : : :
GND : A14 : gnd : : : :
GND : A15 : gnd : : : :
NC : A16 : : : : :
VCCIO3 : A17 : power : : 3.3V : 3 :
high[6] : A18 : output : LVTTL : : 3 : Y
high[3] : A19 : output : LVTTL : : 3 : Y
low[4] : A20 : output : LVTTL : : 3 : Y
low[2] : A21 : output : LVTTL : : 3 : Y
RESERVED_INPUT : A22 : : : : 3 :
RESERVED_INPUT : A23 : : : : 3 :
RESERVED_INPUT : A24 : : : : 3 :
RESERVED_INPUT : A25 : : : : 3 :
RESERVED_INPUT : A26 : : : : 3 :
VCCIO3 : A27 : power : : 3.3V : 3 :
RESERVED_INPUT : AA1 : : : : 6 :
RESERVED_INPUT : AA2 : : : : 6 :
RESERVED_INPUT : AA3 : : : : 6 :
RESERVED_INPUT : AA4 : : : : 6 :
NC : AA5 : : : : :
NC : AA6 : : : : :
NC : AA7 : : : : :
NC : AA8 : : : : :
NC : AA9 : : : : :
NC : AA10 : : : : :
RESERVED_INPUT : AA11 : : : : 7 :
VCCSEL : AA12 : : : : 7 :
VCCG_PLL6 : AA13 : power : : 1.5V : 1 :
RESERVED_INPUT : AA14 : : : : 11 :
RESERVED_INPUT : AA15 : : : : 11 :
GND : AA16 : gnd : : : :
GND+ : AA17 : : : : 8 :
RESERVED_INPUT : AA18 : : : : 8 :
RESERVED_INPUT : AA19 : : : : 8 :
RESERVED_INPUT : AA20 : : : : 8 :
NC : AA21 : : : : :
NC : AA22 : : : : :
NC : AA23 : : : : :
NC : AA24 : : : : :
RESERVED_INPUT : AA25 : : : : 1 :
RESERVED_INPUT : AA26 : : : : 1 :
RESERVED_INPUT : AA27 : : : : 1 :
RESERVED_INPUT : AA28 : : : : 1 :
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