counter_7seg.qsf

带分频器的bcd计数电路设计

# Copyright (C) 1991-2005 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		counter_7seg_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.2 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:29  MARCH 25, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION "4.2 SP1"
set_global_assignment -name VERILOG_FILE f50MHz_to_1Hz.v
set_global_assignment -name VECTOR_WAVEFORM_FILE counter_7seg.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE counter_7seg1.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE counter_7seg2.vwf
set_global_assignment -name VERILOG_FILE decoder_7seg_new.v
set_global_assignment -name VECTOR_WAVEFORM_FILE counter_7seg3.vwf
set_global_assignment -name BDF_FILE counter_7seg.bdf
set_global_assignment -name VERILOG_FILE bcd_counter.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_K17 -to clk
set_location_assignment PIN_W5 -to clr
set_location_assignment PIN_A18 -to high[6]
set_location_assignment PIN_C18 -to high[5]
set_location_assignment PIN_D18 -to high[4]
set_location_assignment PIN_A19 -to high[3]
set_location_assignment PIN_B19 -to high[2]
set_location_assignment PIN_C19 -to high[1]
set_location_assignment PIN_E19 -to high[0]
set_location_assignment PIN_B18 -to low[6]
set_location_assignment PIN_B20 -to low[5]
set_location_assignment PIN_A20 -to low[4]
set_location_assignment PIN_C20 -to low[3]
set_location_assignment PIN_A21 -to low[2]
set_location_assignment PIN_B21 -to low[1]
set_location_assignment PIN_C21 -to low[0]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Stratix
set_global_assignment -name TOP_LEVEL_ENTITY counter_7seg

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1S10F780C6
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name DEVICE_MIGRATION_LIST EP1S10F780C6
set_instance_assignment -name IO_STANDARD LVTTL -to clk

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_INPUT_SOURCE counter_7seg.vwf

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off