counter_7seg.map.eqn

带分频器的bcd计数电路设计

--C1_cn is bcd_counter:inst4|cn
--operation mode is normal

C1_cn_lut_out = C1L51 & C1_cn # !C1L41;
C1_cn = DFFEAS(C1_cn_lut_out, B1_count2[9], !clr, , , , , , );


--C1_high[0] is bcd_counter:inst4|high[0]
--operation mode is normal

C1_high[0]_lut_out = !C1_high[0];
C1_high[0] = DFFEAS(C1_high[0]_lut_out, B1_count2[9], !clr, , C1L51, , , , );


--C1_high[1] is bcd_counter:inst4|high[1]
--operation mode is normal

C1_high[1]_lut_out = C1_high[1] & !C1_high[0] # !C1_high[1] & C1_high[0] & C1_high[2] # !C1_high[3];
C1_high[1] = DFFEAS(C1_high[1]_lut_out, B1_count2[9], !clr, , C1L51, , , , );


--C1_high[2] is bcd_counter:inst4|high[2]
--operation mode is normal

C1_high[2]_lut_out = !C1_high[2];
C1_high[2] = DFFEAS(C1_high[2]_lut_out, B1_count2[9], !clr, , C1L7, , , , );


--C1_high[3] is bcd_counter:inst4|high[3]
--operation mode is normal

C1_high[3]_lut_out = C1_high[3] & C1_high[1] $ C1_high[2] # !C1_high[0] # !C1_high[3] & C1_high[1] & C1_high[2] & C1_high[0];
C1_high[3] = DFFEAS(C1_high[3]_lut_out, B1_count2[9], !clr, , C1L51, , , , );


--D1L7 is decoder_7seg_new:inst5|segment[6]~29
--operation mode is normal

D1L7 = C1_high[1] & C1_high[3] # !C1_high[1] & C1_high[2] $ (C1_high[0] & !C1_high[3]);


--D1L6 is decoder_7seg_new:inst5|segment[5]~31
--operation mode is normal

D1L6 = C1_high[2] & C1_high[3] # C1_high[0] $ C1_high[1] # !C1_high[2] & C1_high[1] & C1_high[3];


--D1L5 is decoder_7seg_new:inst5|segment[4]~33
--operation mode is normal

D1L5 = C1_high[2] & C1_high[3] # !C1_high[2] & C1_high[1] & C1_high[3] # !C1_high[0];


--D1L1 is decoder_7seg_new:inst5|reduce_or~55
--operation mode is normal

D1L1 = C1_high[1] & C1_high[3] # C1_high[0] & C1_high[2] # !C1_high[1] & C1_high[2] $ (C1_high[0] & !C1_high[3]);


--D1L2 is decoder_7seg_new:inst5|reduce_or~57
--operation mode is normal

D1L2 = C1_high[0] # C1_high[1] & C1_high[3] # !C1_high[1] & C1_high[2];


--D1L3 is decoder_7seg_new:inst5|reduce_or~59
--operation mode is normal

D1L3 = C1_high[0] & C1_high[1] # C1_high[2] $ !C1_high[3] # !C1_high[0] & C1_high[2] & C1_high[3] # !C1_high[2] & C1_high[1];


--D1L4 is decoder_7seg_new:inst5|reduce_or~61
--operation mode is normal

D1L4 = C1_high[1] & !C1_high[3] & !C1_high[2] # !C1_high[0] # !C1_high[1] & C1_high[2] $ C1_high[3];


--C1_low[0] is bcd_counter:inst4|low[0]
--operation mode is normal

C1_low[0]_lut_out = !C1_low[0];
C1_low[0] = DFFEAS(C1_low[0]_lut_out, B1_count2[9], !clr, , , , , , );


--C1_low[1] is bcd_counter:inst4|low[1]
--operation mode is normal

C1_low[1]_lut_out = C1_low[1] & !C1_low[0] # !C1_low[1] & C1_low[0] & C1_low[2] # !C1_low[3];
C1_low[1] = DFFEAS(C1_low[1]_lut_out, B1_count2[9], !clr, , , , , , );


--C1_low[2] is bcd_counter:inst4|low[2]
--operation mode is normal

C1_low[2]_lut_out = !C1_low[2];
C1_low[2] = DFFEAS(C1_low[2]_lut_out, B1_count2[9], !clr, , C1L1, , , , );


--C1_low[3] is bcd_counter:inst4|low[3]
--operation mode is normal

C1_low[3]_lut_out = C1_low[3] & C1_low[1] $ C1_low[2] # !C1_low[0] # !C1_low[3] & C1_low[1] & C1_low[2] & C1_low[0];
C1_low[3] = DFFEAS(C1_low[3]_lut_out, B1_count2[9], !clr, , , , , , );


--D2L7 is decoder_7seg_new:inst6|segment[6]~29
--operation mode is normal

D2L7 = C1_low[1] & C1_low[3] # !C1_low[1] & C1_low[2] $ (C1_low[0] & !C1_low[3]);


--D2L6 is decoder_7seg_new:inst6|segment[5]~31
--operation mode is normal

D2L6 = C1_low[2] & C1_low[3] # C1_low[0] $ C1_low[1] # !C1_low[2] & C1_low[1] & C1_low[3];


--D2L5 is decoder_7seg_new:inst6|segment[4]~33
--operation mode is normal

D2L5 = C1_low[2] & C1_low[3] # !C1_low[2] & C1_low[1] & C1_low[3] # !C1_low[0];


--D2L1 is decoder_7seg_new:inst6|reduce_or~55
--operation mode is normal

D2L1 = C1_low[1] & C1_low[3] # C1_low[0] & C1_low[2] # !C1_low[1] & C1_low[2] $ (C1_low[0] & !C1_low[3]);


--D2L2 is decoder_7seg_new:inst6|reduce_or~57
--operation mode is normal

D2L2 = C1_low[0] # C1_low[1] & C1_low[3] # !C1_low[1] & C1_low[2];


--D2L3 is decoder_7seg_new:inst6|reduce_or~59
--operation mode is normal

D2L3 = C1_low[0] & C1_low[1] # C1_low[2] $ !C1_low[3] # !C1_low[0] & C1_low[2] & C1_low[3] # !C1_low[2] & C1_low[1];


--D2L4 is decoder_7seg_new:inst6|reduce_or~61
--operation mode is normal

D2L4 = C1_low[1] & !C1_low[3] & !C1_low[2] # !C1_low[0] # !C1_low[1] & C1_low[2] $ C1_low[3];


--C1L41 is bcd_counter:inst4|reduce_nor~41
--operation mode is normal

C1L41 = C1_high[1] # C1_high[2] # !C1_high[3] # !C1_high[0];


--C1L51 is bcd_counter:inst4|reduce_nor~42
--operation mode is normal

C1L51 = !C1_low[1] & !C1_low[2] & C1_low[0] & C1_low[3];


--B1_count2[9] is f50MHz_to_1Hz:inst|count2[9]
--operation mode is normal

B1_count2[9]_lut_out = B1L91 & B1L18;
B1_count2[9] = DFFEAS(B1_count2[9]_lut_out, B1L15Q, VCC, , , , , , );


--C1L7 is bcd_counter:inst4|high[2]~108
--operation mode is normal

C1L7 = C1_high[0] & C1_high[1] & C1L51;


--C1L1 is bcd_counter:inst4|add~109
--operation mode is normal

C1L1 = C1_low[0] & C1_low[1];


--B1L91 is f50MHz_to_1Hz:inst|add~271
--operation mode is normal

B1L91_carry_eqn = B1L81;
B1L91 = B1_count2[9] $ (B1L91_carry_eqn);


--B1_count2[8] is f50MHz_to_1Hz:inst|count2[8]
--operation mode is normal

B1_count2[8]_lut_out = B1L71 & B1L18;
B1_count2[8] = DFFEAS(B1_count2[8]_lut_out, B1L15Q, VCC, , , , , , );


--B1_count2[7] is f50MHz_to_1Hz:inst|count2[7]
--operation mode is normal

B1_count2[7]_lut_out = B1L51 & B1L18;
B1_count2[7] = DFFEAS(B1_count2[7]_lut_out, B1L15Q, VCC, , , , , , );


--B1_count2[6] is f50MHz_to_1Hz:inst|count2[6]
--operation mode is normal

B1_count2[6]_lut_out = B1L31 & B1L18;
B1_count2[6] = DFFEAS(B1_count2[6]_lut_out, B1L15Q, VCC, , , , , , );


--B1L97 is f50MHz_to_1Hz:inst|reduce_nor~166
--operation mode is normal

B1L97 = !B1_count2[6] # !B1_count2[7] # !B1_count2[8] # !B1_count2[9];


--B1_count2[4] is f50MHz_to_1Hz:inst|count2[4]
--operation mode is normal

B1_count2[4]_lut_out = B1L9;
B1_count2[4] = DFFEAS(B1_count2[4]_lut_out, B1L15Q, VCC, , , , , , );


--B1_count2[3] is f50MHz_to_1Hz:inst|count2[3]
--operation mode is normal

B1_count2[3]_lut_out = B1L7 & B1L18;
B1_count2[3] = DFFEAS(B1_count2[3]_lut_out, B1L15Q, VCC, , , , , , );


--B1_count2[5] is f50MHz_to_1Hz:inst|count2[5]
--operation mode is normal

B1_count2[5]_lut_out = B1L11 & B1L18;
B1_count2[5] = DFFEAS(B1_count2[5]_lut_out, B1L15Q, VCC, , , , , , );


--B1_count2[2] is f50MHz_to_1Hz:inst|count2[2]
--operation mode is normal

B1_count2[2]_lut_out = B1L5;
B1_count2[2] = DFFEAS(B1_count2[2]_lut_out, B1L15Q, VCC, , , , , , );


--B1L08 is f50MHz_to_1Hz:inst|reduce_nor~167
--operation mode is normal

B1L08 = B1_count2[4] # B1_count2[3] # !B1_count2[2] # !B1_count2[5];


--B1_count2[1] is f50MHz_to_1Hz:inst|count2[1]
--operation mode is normal

B1_count2[1]_lut_out = B1L3;
B1_count2[1] = DFFEAS(B1_count2[1]_lut_out, B1L15Q, VCC, , , , , , );


--B1_count2[0] is f50MHz_to_1Hz:inst|count2[0]
--operation mode is normal

B1_count2[0]_lut_out = B1L1;
B1_count2[0] = DFFEAS(B1_count2[0]_lut_out, B1L15Q, VCC, , , , , , );


--B1L18 is f50MHz_to_1Hz:inst|reduce_nor~168
--operation mode is normal

B1L18 = B1L97 # B1L08 # !B1_count2[0] # !B1_count2[1];


--B1L15Q is f50MHz_to_1Hz:inst|clk_1khz~reg0
--operation mode is normal

B1L15Q_lut_out = B1L05 & B1L68;
B1L15Q = DFFEAS(B1L15Q_lut_out, clk, VCC, , , , , , );


--B1L71 is f50MHz_to_1Hz:inst|add~270
--operation mode is arithmetic

B1L71_carry_eqn = B1L61;
B1L71 = B1_count2[8] $ (!B1L71_carry_eqn);

--B1L81 is f50MHz_to_1Hz:inst|add~270COUT
--operation mode is arithmetic

B1L81 = CARRY(B1_count2[8] & !B1L61);


--B1L51 is f50MHz_to_1Hz:inst|add~269
--operation mode is arithmetic

B1L51_carry_eqn = B1L41;
B1L51 = B1_count2[7] $ (B1L51_carry_eqn);

--B1L61 is f50MHz_to_1Hz:inst|add~269COUT
--operation mode is arithmetic

B1L61 = CARRY(!B1L41 # !B1_count2[7]);


--B1L31 is f50MHz_to_1Hz:inst|add~268
--operation mode is arithmetic

B1L31_carry_eqn = B1L21;
B1L31 = B1_count2[6] $ (!B1L31_carry_eqn);

--B1L41 is f50MHz_to_1Hz:inst|add~268COUT
--operation mode is arithmetic

B1L41 = CARRY(B1_count2[6] & !B1L21);


--B1L9 is f50MHz_to_1Hz:inst|add~266
--operation mode is arithmetic

B1L9_carry_eqn = B1L8;
B1L9 = B1_count2[4] $ (!B1L9_carry_eqn);

--B1L01 is f50MHz_to_1Hz:inst|add~266COUT
--operation mode is arithmetic

B1L01 = CARRY(B1_count2[4] & !B1L8);


--B1L7 is f50MHz_to_1Hz:inst|add~265
--operation mode is arithmetic

B1L7_carry_eqn = B1L6;
B1L7 = B1_count2[3] $ (B1L7_carry_eqn);

--B1L8 is f50MHz_to_1Hz:inst|add~265COUT
--operation mode is arithmetic

B1L8 = CARRY(!B1L6 # !B1_count2[3]);


--B1L11 is f50MHz_to_1Hz:inst|add~267
--operation mode is arithmetic

B1L11_carry_eqn = B1L01;
B1L11 = B1_count2[5] $ (B1L11_carry_eqn);

--B1L21 is f50MHz_to_1Hz:inst|add~267COUT
--operation mode is arithmetic

B1L21 = CARRY(!B1L01 # !B1_count2[5]);


--B1L5 is f50MHz_to_1Hz:inst|add~264
--operation mode is arithmetic

B1L5_carry_eqn = B1L4;
B1L5 = B1_count2[2] $ (!B1L5_carry_eqn);

--B1L6 is f50MHz_to_1Hz:inst|add~264COUT
--operation mode is arithmetic

B1L6 = CARRY(B1_count2[2] & !B1L4);


--B1L3 is f50MHz_to_1Hz:inst|add~263
--operation mode is arithmetic

B1L3_carry_eqn = B1L2;
B1L3 = B1_count2[1] $ (B1L3_carry_eqn);

--B1L4 is f50MHz_to_1Hz:inst|add~263COUT
--operation mode is arithmetic

B1L4 = CARRY(!B1L2 # !B1_count2[1]);


--B1L1 is f50MHz_to_1Hz:inst|add~262
--operation mode is arithmetic

B1L1 = !B1_count2[0];

--B1L2 is f50MHz_to_1Hz:inst|add~262COUT
--operation mode is arithmetic

B1L2 = CARRY(B1_count2[0]);


--B1L05 is f50MHz_to_1Hz:inst|add~287
--operation mode is normal

B1L05_carry_eqn = B1L94;
B1L05 = B1L15Q $ (B1L05_carry_eqn);


--B1_count1[13] is f50MHz_to_1Hz:inst|count1[13]
--operation mode is normal

B1_count1[13]_lut_out = B1L64;
B1_count1[13] = DFFEAS(B1_count1[13]_lut_out, clk, VCC, , , , , , );


--B1_count1[12] is f50MHz_to_1Hz:inst|count1[12]
--operation mode is normal

B1_count1[12]_lut_out = B1L44;
B1_count1[12] = DFFEAS(B1_count1[12]_lut_out, clk, VCC, , , , , , );


--B1_count1[14] is f50MHz_to_1Hz:inst|count1[14]