ddsc.vhd

我自己用vhdl实现编的dds

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ddsc is
     generic(freq_width:integer:=32;
             phase_width:integer:=12;
             adder_width:integer:=32;
             romad_width:integer:=8;
             rom_d_width:integer:=8);
 	 port(clk:in std_logic;
          freqin:in std_logic_vector(freq_width-1 downto 0);
          phasein:in std_logic_vector(phase_width-1 downto 0);
 		  dacout:out std_logic_vector(rom_d_width-1 downto 0));
end entity ddsc;

architecture behave of ddsc is
 signal acc:std_logic_vector(adder_width-1 downto 0);
 signal phaseadd:std_logic_vector(phase_width-1 downto 0);
 signal romaddr:std_logic_vector(romad_width-1 downto 0);
 signal freqw:std_logic_vector(freq_width-1 downto 0);
 signal phasew:std_logic_vector(phase_width-1 downto 0);
 signal dsout:std_logic_vector(rom_d_width-1 downto 0);
 signal romaddr1:std_logic_vector(romad_width-3 downto 0);
 signal dac_ff:std_logic_vector(rom_d_width-1 downto 0);
 signal ddsout1,ddsout:std_logic_vector(rom_d_width-1 downto 0);
 signal romaddr_msb1,romaddr_msb2:std_logic;
 component rom
    port(outclock:in std_logic;
         address:in std_logic_vector(5 downto 0);
         q:out std_logic_vector(7 downto 0));
 end component;
begin 
   process(clk)
   begin
    if(clk'event and clk='1')then
       freqw<=freqin;
       phasew<=phasein;
       acc<=acc+freqw;
    end if;
   end process;

   phaseadd<=acc(adder_width-1 downto adder_width-phase_width)+phasew;
   romaddr<=phaseadd(phase_width-1 downto phase_width-romad_width);
         process(clk)
        begin
          if (clk 'event and clk='1') then 
             romaddr_msb1<=romaddr(romad_width-1);
             romaddr_msb2<=romaddr_msb1;
             ddsout1<=ddsout;
             if (romaddr(romad_width-2)='1') then
                   romaddr1<=not(romaddr(romad_width-3 downto 0));
             else
                   romaddr1<=romaddr(romad_width-3 downto 0);
             end if;
             dac_ff(rom_d_width-1)<=not(romaddr_msb2);
             if (romaddr_msb2='1') then
                 dac_ff(rom_d_width-2 downto 0)<=not(ddsout1);
             else 
                 dac_ff(rom_d_width-2 downto 0)<=ddsout1;
             end if;
          end if;
	  end process;
          dacout<=dac_ff;
end architecture behave;