fifowr.tdf

这是用AHDL语言编写的一个PCI采集系统的逻辑源码

SUBDESIGN fifowr
(
--add on interface
	/ptatn						:	INPUT;
	/ptburst					:	INPUT;
	ptwr						:	INPUT;
	bpclk						:	INPUT;
	/sysrst						:	INPUT;
 	/select						:	OUTPUT;
 	/wr							:	OUTPUT;
	/rd							:	OUTPUT;
	mode						:	OUTPUT;
	/ptrdy						:	OUTPUT;
	/ptadr						:	OUTPUT;
	/be[3..0]					:	OUTPUT;
	adr[6..2]					:	OUTPUT;
 	dq[31..0]					:	BIDIR;

--fifo interface signals
    wrfull						:	INPUT;
	wrfifo						:	OUTPUT;

--nonvalid signals
	rdfifo						:	OUTPUT;

-- interface with 10k208
	trans_data[7..0] 			:	BIDIR ;
	nvsram_write_oe  			:	OUTPUT;
	write_addr[16..0] 			: 	OUTPUT;
	nvsram_wr				 	: 	OUTPUT;
	valid					 	: 	INPUT; -- sample data is availble,ready transfor from 10k208 to 10k144
	clkout						: 	OUTPUT; -- bpclk
	req							: 	OUTPUT;  --wrfull
	CESHI                       :   OUTPUT;
)

VARIABLE
	data_to_s5933[31..0]		:	TRI;
	read_data_from_sram[31..0] 	: 	DFF;
	wrfifo						: 	dff;
	dq_oe 						: 	DFF;
	data_count[7..0]           	:   dff; 
	nvsram_write_oe 			: 	DFF;
	nvsram_wr 					: 	DFF;
	nvsram_write_data[7..0]		:	TRI;
	data_oe 					:	DFF;
	cs 							: 	NODE;
	pt_ctrl						: 	MACHINE 
 									OF BITS (/select, adr[6..2], /be[3..0],/ptadr,/ptrdy,/rd,/wr,fifo_oe)
 									WITH STATES 
									(
 										idle =  B"100000111111111",
 										addr =  B"001011000001110",
 										write = B"001011000011010",    --PCI write, addon read
 										read =  B"001011000011100",
 										ready=  B"001011000010110",
        								turn=   B"101011111111110",	
										wait0=  B"001011000010110",
										wait1=  B"101011111111110",
										wait2=  B"101011111111110"
									);
 	data_to_nvsram[31..0]		: 	DFFE;
	addr_to_nvsram[31..0]		: 	DFFE; 

	asm_ctrl					: 	MACHINE WITH STATES
									(
										asm_idle,asm_stuff,
								  		asm_wait_one,asm_wait_two,
								  		asm_work_idle,asm_work_byte0,
										asm_wait0,asm_work_byte1,
								  		asm_wait1,asm_work_byte2,
										asm_wait2,asm_work_byte3,
										asm_turn
									);
BEGIN

	rdfifo = VCC;
	CESHI = vcc;

	clkout = bpclk;
	req = wrfull;

	mode = GND; --32 bit mode
	
	wrfifo.clk = !bpclk;
	dq_oe.clk = bpclk; -- when write fifo, dq[] is enable to be written
	read_data_from_sram[].clk = bpclk;

 	data_to_s5933[].oe = dq_oe;
 	data_to_s5933[].in = read_data_from_sram[];
 	dq[] = data_to_s5933[].out;

 	data_to_nvsram[].clk = bpclk;
 	data_to_nvsram[].ENA = !/rd;
 	addr_to_nvsram[].clk = bpclk;
 	addr_to_nvsram[].ena = !/ptadr;

	write_addr[16..0] = addr_to_nvsram[16..0];
	
	data_count[].clk = bpclk;


 	data_oe.clk = bpclk;
	nvsram_wr.clk = bpclk;
	pt_ctrl.clk = bpclk;
 	pt_ctrl.reset = !/sysrst;
  
	TABLE
 		pt_ctrl,	/ptatn,    ptwr	   =>  pt_ctrl,	 nvsram_wr,	data_oe;
 
 		idle,       1,         x       =>  idle,		1,			0;
 		idle,       0,         x       =>  addr,		1,			0;
 		addr,       0,         1       =>  write,		0,			1;
 		addr,       0,         0       =>  read,		1,			0;
 		write,      x,         x       =>  wait0,		0,			1;	 
 		wait0,      x,         x       =>  wait1,		0,			1;	 
 		wait1,      x,         x       =>  wait2,		0,			1;	 
 		wait2,      x,         x       =>  turn,		1,			1;	 
 		read,       x,         x       =>  ready,		1,			0; 
  		ready,      x,         x       =>  turn,		1,			0;
  		turn,       x,         x       =>  idle,		1,			0;
 	END TABLE;


 	IF pt_ctrl == addr THEN
   	 	addr_to_nvsram[] = dq[];
 	END IF; 

 	IF pt_ctrl == write THEN
   		data_to_nvsram[] = dq[];
 	END IF;    

	cs = (addr_to_nvsram[] == H"10000");
	nvsram_write_oe.clk  = !cs;
	nvsram_write_oe = data_to_nvsram0; -- when PC write address"H10000" for data"1", indicate now begin to write nvsram

	nvsram_write_data[].oe = data_oe;
	nvsram_write_data[].in = data_to_nvsram[7..0];
	trans_data[] = nvsram_write_data[].out;


	asm_ctrl.clk = bpclk;
	asm_ctrl.reset= GND;
	IF(!fifo_oe) THEN 		-- add on bus is working, 
		wrfifo = VCC;
		dq_oe = GND; 		-- not put fifo data onto dq bus
		asm_ctrl = asm_idle;
	ELSE					-- may operate fifo write, add on bus is idle
		CASE asm_ctrl IS
			WHEN asm_idle =>
				wrfifo = VCC;
				dq_oe = GND; -- not put fifo data onto dq bus
				data_count[] = 0;
				asm_ctrl = asm_stuff;
			WHEN asm_stuff =>
				dq_oe = VCC;
				wrfifo = GND;
				data_count[] = 0;
				read_data_from_sram[] = 88888888;
				asm_ctrl = asm_wait_one;
			WHEN asm_wait_one =>
				dq_oe = VCC;
				wrfifo = VCC;
				data_count[] = 0;
				read_data_from_sram[] = 88888888;
				asm_ctrl = asm_wait_two;
			WHEN asm_wait_two =>
				wrfifo = VCC;
				dq_oe = GND;
				data_count[] = 0;
				read_data_from_sram[] = read_data_from_sram[];
				IF(wrfull) THEN
					asm_ctrl=asm_work_idle;
				ELSE
					asm_ctrl=asm_stuff;
				END IF;
			WHEN asm_work_idle =>
				wrfifo = VCC;
				dq_oe = GND;
				data_count[] = data_count[];
				read_data_from_sram[] = 0; 
				IF(valid) THEN
					asm_ctrl = asm_work_byte0;
				ELSE
					asm_ctrl = asm_work_idle;
				END IF;
			WHEN asm_work_byte0 =>
				wrfifo = VCC;
				dq_oe = GND;
				data_count[] = data_count[] + 1;
				--read_data_from_sram[7..0] = data_count[7..0];
				read_data_from_sram[7..0] = trans_data[7..0];
				read_data_from_sram[31..8] = 0;					
				asm_ctrl = asm_wait0;
			WHEN asm_wait0 =>
				wrfifo = VCC;
				dq_oe = GND;
				data_count[] = data_count[];
				read_data_from_sram[7..0] = read_data_from_sram[7..0];
				read_data_from_sram[31..8] = 0;
				IF(valid) THEN
					asm_ctrl = asm_work_byte1;
				ELSE
					asm_ctrl = asm_wait0;
				END IF;
			WHEN asm_work_byte1 =>
				wrfifo = VCC;
				dq_oe = GND;
				read_data_from_sram[7..0] = read_data_from_sram[7..0];
				--read_data_from_sram[15..8] = data_count[7..0];
				read_data_from_sram[15..8] = trans_data[7..0];
				read_data_from_sram[31..16] = 0;
				data_count[] = data_count[] + 1;
				asm_ctrl = asm_wait1;
			WHEN asm_wait1 =>
				wrfifo = VCC;
				dq_oe = GND;
				data_count[] = data_count[];
				read_data_from_sram[15..0] = read_data_from_sram[15..0];
				read_data_from_sram[31..16] = 0;
				IF(valid) THEN
					asm_ctrl = asm_work_byte2;
				ELSE
					asm_ctrl = asm_wait1;
				END IF;
			WHEN asm_work_byte2 =>
				wrfifo = VCC;
				dq_oe = GND; 
				data_count[] = data_count[] + 1;
				read_data_from_sram[15..0] = read_data_from_sram[15..0];
				--read_data_from_sram[23..16] = data_count[7..0];
				read_data_from_sram[23..16] = trans_data[7..0];
				read_data_from_sram[31..24] = 0;
				asm_ctrl = asm_wait2;
			WHEN asm_wait2 =>
				wrfifo = VCC;
				dq_oe = GND;
				data_count[] = data_count[];
				read_data_from_sram[23..0] = read_data_from_sram[23..0];
				read_data_from_sram[31..24] = 0;
				IF(valid) THEN
					asm_ctrl = asm_work_byte3;
				ELSE
					asm_ctrl = asm_wait2;
				END IF;
			WHEN asm_work_byte3 =>
				wrfifo = vcc;   -- begin to write fifo
				dq_oe = VCC;   -- begin put data onto dq[] bus
				data_count[] = data_count[] + 1;
				read_data_from_sram[23..0] = read_data_from_sram[23..0];
				--read_data_from_sram[31..24] = data_count[7..0];	
				read_data_from_sram[31..24] = trans_data[7..0];
				asm_ctrl = asm_turn;
			WHEN asm_turn=>
				wrfifo = gnd;
				dq_oe = VCC;
				data_count[] = data_count[];
				read_data_from_sram[] = read_data_from_sram[];
				asm_ctrl = asm_work_idle;
		END CASE;
	END IF;
END;