vsr_4_3_rx_all.v

甚短距离互联（Veryshort reach VSR）协议编成实现

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  vsr_4_03	the whole module of the rx direction		 ////
////                                                             ////
////  Author: liyu	                                         ////
////          [e-mail]                              ////
////          		                                         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 liyu                        		 ////
////                    [e-mail]                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module	vsr_4_3_rx_all(
		din_0,
		din_1,
		din_2,
		din_3,
		clk_155a,
		clk_155b,
		clk_155c,
		clk_155d,
		rst,
		sync_state,
		dout
		);

input	[15:0]	din_0;
input	[15:0]	din_1;
input	[15:0]	din_2;
input	[15:0]	din_3;
input		clk_155a;
input		clk_155b;
input		clk_155c;
input		clk_155d;
input		rst;

output	[63:0]	dout;
output	[2:0]	sync_state;

wire	[15:0]	aligned_data0;
wire	[15:0]	aligned_data1;
wire	[15:0]	aligned_data2;
wire	[15:0]	aligned_data3;
wire		fr_pattern0;
wire		fr_pattern1;
wire		fr_pattern2;
wire		fr_pattern3;
wire	[2:0]	sync_state;
wire	[3:0]	fr;
wire		oof0;
wire		oof1;
wire		oof2;
wire		oof3;


vsr_4_3_receiver_frame_syn	framer0(
 					.din(din_0),
 					.dout(aligned_data0),
 					.rst(rst),
 					.clk(clk_155a),
 					.fr(fr[0]),
 					.oof(oof0),
 					.fr_pattern(fr_pattern0)
 					);

vsr_4_3_receiver_frame_syn	framer1(
 					.din(din_1),
 					.dout(aligned_data1),
 					.rst(rst),
 					.clk(clk_155b),
 					.fr(fr[1]),
 					.oof(oof1),
 					.fr_pattern(fr_pattern1)
 					);
 
vsr_4_3_receiver_frame_syn	framer2(
 					.din(din_2),
 					.dout(aligned_data2),
 					.rst(rst),
 					.clk(clk_155c),
 					.fr(fr[2]),
 					.oof(oof2),
 					.fr_pattern(fr_pattern2)
 					);
vsr_4_3_receiver_frame_syn	framer3(
 					.din(din_3),
 					.dout(aligned_data3),
 					.rst(rst),
 					.clk(clk_155d),
 					.fr(fr[3]),
 					.oof(oof3),
 					.fr_pattern(fr_pattern3)
 					); 
 					
 vsr_4_3_rx_state	rx_state_m(
				.ch0_pattern(fr_pattern0),
				.ch1_pattern(fr_pattern1),
				.ch2_pattern(fr_pattern2),
				.ch3_pattern(fr_pattern3),
				.ch0_oof(oof0),
				.ch1_oof(oof1),
				.ch2_oof(oof2),
				.ch3_oof(oof3),
				.sync_state(sync_state),
				.clk0(clk_155a),
				.clk1(clk_155b),
				.clk2(clk_155c),
				.clk3(clk_155d),
				.rst(rst)
				); 	
				
vsr_4_3_alignment_buffer	deskew_buffer(
					.din0(aligned_data0),
					.din1(aligned_data1),
					.din2(aligned_data2),
					.din3(aligned_data3),
					.fr0(fr[0]),
					.fr1(fr[1]),
					.fr2(fr[2]),
					.fr3(fr[3]),
					.syn_state(sync_state),
					.dout(dout),
					.clk0(clk_155a),
					.clk1(clk_155b),
					.clk2(clk_155c),
					.clk3(clk_155d),
					.rst(rst)
					);								
 																										 					
endmodule