vsr_4_3_tx_buffer.v

甚短距离互联（Veryshort reach VSR）协议编成实现

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  vsr_4_03	change the width of the data path		 ////
////                                                             ////
////  Author: liyu	                                         ////
////          [e-mail]                              ////
////          		                                         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 liyu                        		 ////
////                    [e-mail]                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on

module vsr_4_3_buffer(din,dout,clk_155,clk_124,rst,fr);
input	[15:0]	din;
input		clk_155;
input		clk_124;
input		rst;
input		fr;
output	[19:0]	dout;

reg	[15:0]	da0;
reg	[15:0]	db0;
reg	[15:0]	dc0;
reg	[15:0]	dd0;
reg	[15:0]	de0;
reg	[15:0]	da1;
reg	[15:0]	db1;
reg	[15:0]	dc1;
reg	[15:0]	dd1;
reg	[15:0]	de1;

reg	[3:0]	sel;
reg		a_or_b;
always@(posedge clk_155 or posedge rst)
begin
	if (rst) begin
		sel<=4'b0000;
		a_or_b<=1'b0;
	end	
	else begin
		if (fr) begin
			sel<=4'b0000;
			a_or_b<=1'b0;
		end	
		else begin
			case(sel)
			4'b0000: sel<=4'b0001;
			4'b0001: sel<=4'b0010;
			4'b0010: sel<=4'b0100;
			4'b0100: sel<=4'b1000;	
			4'b1000: begin
				sel<=4'b0000;
				a_or_b<=~a_or_b;
			end	
			default: begin
				sel<=4'b0000;
				a_or_b<=1'b0;
			end	
			endcase
		end		
	end		
end	

always@(posedge clk_155)
begin
	if (sel==4'b0000&&!a_or_b)
		da0<=din;
	if (sel==4'b0001&&!a_or_b)
		db0<=din;
	if (sel==4'b0010&&!a_or_b)
		dc0<=din;
	if (sel==4'b0100&&!a_or_b)
		dd0<=din;	
	if (sel==4'b1000&&!a_or_b)
		de0<=din;	
	if (sel==4'b0000&&a_or_b)
		da1<=din;	
	if (sel==4'b0001&&a_or_b)
		db1<=din;	
	if (sel==4'b0010&&a_or_b)
		dc1<=din;
	if (sel==4'b0100&&a_or_b)
		dd1<=din;
	if (sel==4'b1000&&a_or_b)
		de1<=din;								
end	

reg	[19:0]	ra,rb;
reg	[2:0]	sle;

always@(posedge clk_124 or posedge rst)
begin
	if (rst) 
		sle<=3'b000;	
	else begin
		case(sle)
		3'b000: sle<=3'b001;
		3'b001: sle<=3'b010;
		3'b010: sle<=3'b100;
		3'b100: sle<=3'b000;
		default: sle<=3'b000;
		endcase
	end			
end	

reg	fra;

always@(posedge clk_124)
begin
		case(sle)
		3'b000: ra<={da0,	db0[15:12]};
		3'b001: ra<={db0[11:0],	dc0[15:8]};
		3'b010: ra<={dc0[7:0],	dd0[15:4]};
		3'b100: ra<={dd0[3:0],	de0[15:0]};
		endcase
end	

always@(posedge clk_124)
begin	
		case(sle)
		3'b000: rb<={da1,	db1[15:12]};
		3'b001: rb<={db1[11:0],	dc1[15:8]};
		3'b010: rb<={dc1[7:0],	dd1[15:4]};
		3'b100: rb<={dd1[3:0],	de1[15:0]};
		endcase	
end	

always@(posedge clk_124)
begin
  if (sle==3'b000)
	fra<=a_or_b;
end	
assign	dout=(fra)?ra:rb;

endmodule