📄 vsr_4_3_tx_binary_search.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// vsr_4_03 binary search for the a1a2 boundary ////
//// ////
//// Author: liyu ////
//// acousticdream@163.com ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 liyu ////
//// acousticdream@163.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module vsr_4_3_tx_binary_search(din,sel,clk,rst);
input [62:0] din;
output [5:0] sel;
input clk;
input rst;
reg [30:0] da;
reg [14:0] db;
reg [6:0] dc;
reg [2:0] dd;
reg de;
always@(posedge clk or posedge rst)
begin
if (rst) begin
da<=30'b0;
db<=15'b0;
dc<=7'b0;
dd<=3'b0;
de<=1'b0;
end
else begin
da<=(din[32:31])?din[62:32] :din[30:0];
db<=( da[16:15])? da[30:16] : da[14:0];
dc<=( db[8:7] )? db[14:8] : db[6:0] ;
dd<=( dc[4:3] )? dc[6:4] : dc[2:0] ;
de<=( dd[2:1] )? dd[2] : dd[0] ;
end
end
wire [5:0] control;
assign control[5]=(din[32:31])?1'b1:1'b0;
assign control[4]=( da[16:15])?1'b1:1'b0;
assign control[3]=( db[8:7] )?1'b1:1'b0;
assign control[2]=( dc[4:3] )?1'b1:1'b0;
assign control[1]=( dd[2:1] )?1'b1:1'b0;
assign control[0]=de;
reg [5:0] sel;
always@(posedge clk or posedge rst)
begin
if (rst) begin
sel<=6'b000000;
end
else begin
sel<=control;
end
end
endmodule
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