vsr_4_3_transmit_frame_syn.v

甚短距离互联（Veryshort reach VSR）协议编成实现

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  vsr_4_03	transmit path frame synchronization              ////
////                                                             ////
////  Author: liyu	                                         ////
////          [e-mail]                              ////
////          		                                         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2004 liyu                        		 ////
////                    [e-mail]                    ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//synopsys translate_off
`include "timescale.v"
//synopsys translate_on

module vsr_4_3_transmit_frame_syn(
			din,
			dout,
			rst,
			clk,
			fr,
			lock
			);
parameter	STATE_OOF=5'b00000,
		MATCH_ONE=5'b00001,
		STATE_SYN=5'b00010,
		LOST_ONEF=5'b00100,
		LOST_TWOF=5'b01000,
		LOST_THRF=5'b10000;
parameter	NA=16,
		NB=8;		
		
input	[63:0]	din;
output	[63:0]	dout;
input		clk;
input		rst;
output		fr;
output		lock;

//
//internal regs and wires
//

wire		done;
wire		well;
wire	[63:0]	aligned_data;	
reg		load;
reg	[5:0]	delay;

reg	[4:0]	state;
reg	[14:0]	fcount;
wire	[14:0]	n=15'd63;
wire	[14:0]	nop=15'd38;

//wire	[14:0]	n=15'd19440;
//wire	[14:0]	nop=15'd19416;

wire	match_a1;
wire	match_a2;
reg	match_a1_reg;
wire	match_all=(match_a1_reg&&match_a2)?1'b1:1'b0;
vsr_4_3_pattern_compare	comp_a1(.din(aligned_data[NA-1:0]),.dout(match_a1));
defparam		comp_a1.WIDTH=NA,
			comp_a1.KEY={(NA/8){8'hf6}};

vsr_4_3_pattern_compare	comp_a2(.din(aligned_data[63:64-NA]),.dout(match_a2));
defparam		comp_a2.WIDTH=NA,
			comp_a2.KEY={(NA/8){8'h28}};	
			
always@(posedge clk or posedge rst)
begin
	if (rst)
		match_a1_reg<=1'b0;
	else 
		match_a1_reg<=match_a1;	
end						

vsr_4_3_tx_aligner		fisrt_stage(.din(din),.dout(aligned_data),.load(!load),.rst(rst),.clk(clk),.done(done));


always@(posedge clk or posedge rst)
begin
	if (rst)
		delay<=6'b000000;
	else begin
		delay[5:1]<=delay[4:0];
		delay[0]<=done;
	end		
end	

assign		well=delay[5];
assign		dout=aligned_data;

always@(posedge clk or posedge rst)
begin
	if (rst)
		fcount<=15'b000000000000000;
	else begin
		if ((match_all&&state==5'b00000)||(fcount==n))
			fcount<=15'b000000000000000;
		else
			fcount<=fcount+15'b1;	
	end		
end	

reg	[2:0]	watchdog;
always@(posedge clk or posedge rst)
begin
	if (rst)
		watchdog<=3'b000;
	else begin
		if (watchdog==3'b101)
			watchdog<=3'b000;
		else begin	
			if (fcount==n)
				watchdog<=watchdog+3'b001; 
		end		
	end	 			
end	

always@(posedge clk or posedge rst)
begin
	if (rst) begin
		state<=STATE_OOF;
		load<=1'b0;
	end	
	else begin
		case(state)
		STATE_OOF: begin
			if (match_all&&well)
				state<=MATCH_ONE;
			if (watchdog==3'b101)	
				load<=1'b0;
			else
				load<=1'b1;					
		end
		MATCH_ONE: begin
			if (match_all&&fcount==n)
				state<=STATE_SYN;
			else if (!match_all&&fcount==n)
				state<=STATE_OOF;
		end			
		STATE_SYN: begin		
			if (!match_all&&fcount==n)
				state<=LOST_ONEF;
		end		
		LOST_ONEF: begin
			if (match_all&&fcount==n)
				state<=STATE_SYN;
			else if (!match_all&&fcount==n)
				state<=LOST_TWOF;
		end	
		LOST_TWOF: begin
			if (match_all&&fcount==n)
				state<=STATE_SYN;
			else if (!match_all&&fcount==n)
				state<=LOST_THRF;
		end		
		LOST_THRF: begin
			if (match_all&&fcount==n)
				state<=STATE_SYN;
			else if (!match_all&&fcount==n) begin
				load<=1'b0;
				state<=STATE_OOF;
			end	
		end	
		default: begin
			state<=STATE_OOF;
		end			
		endcase
	end	
end	

wire	fr=((fcount==nop)&&lock);
wire	lock=(state==5'b00010)?1'b1:1'b0;

endmodule