signal.fit.qmsg

一个简单的多种信号的发生器 包括正玄

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 07 22:46:50 2006 " "Info: Processing started: Tue Mar 07 22:46:50 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off signal -c signal " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off signal -c signal" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "signal EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"signal\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "1 13 " "Info: No exact pin location assignment(s) for 1 pins of 13 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[2\] " "Info: Pin sel\[2\] not assigned to an exact location on the device" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } } { "d:/quartus5/bin/Assignment Editor.qase" "" { Assignment "d:/quartus5/bin/Assignment Editor.qase" 1 { { 0 "sel\[2\]" } } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { sel[2] } "NODE_NAME" } "" } } { "F:/myproject/信号发生器/signal/signal.fld" "" { Floorplan "F:/myproject/信号发生器/signal/signal.fld" "" "" { sel[2] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 14 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 14" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "selectsignal:inst7\|Mux~520 Global clock " "Info: Automatically promoted signal \"selectsignal:inst7\|Mux~520\" to use Global clock" {  } { { "d:/quartus5/bin/Assignment Editor.qase" "" { Assignment "d:/quartus5/bin/Assignment Editor.qase" 1 { { 0 "selectsignal:inst7\|Mux~520" } } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { selectsignal:inst7|Mux~520 } "NODE_NAME" } "" } } { "F:/myproject/信号发生器/signal/signal.fld" "" { Floorplan "F:/myproject/信号发生器/signal/signal.fld" "" "" { selectsignal:inst7|Mux~520 } "NODE_NAME" } }  } 0}