signal.map.qmsg

一个简单的多种信号的发生器 包括正玄

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 07 22:46:43 2006 " "Info: Processing started: Tue Mar 07 22:46:43 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off signal -c signal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off signal -c signal" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "selectsignal.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file selectsignal.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 selectsignal-a " "Info: Found design unit 1: selectsignal-a" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 selectsignal " "Info: Found entity 1: selectsignal" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal1.vhdl 2 1 " "Info: Found 2 design units, including 1 entities, in source file signal1.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 signal1-a " "Info: Found design unit 1: signal1-a" {  } { { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 signal1 " "Info: Found entity 1: signal1" {  } { { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal2.vhdl 2 1 " "Info: Found 2 design units, including 1 entities, in source file signal2.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 signal2-a " "Info: Found design unit 1: signal2-a" {  } { { "signal2.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal2.vhdl" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 signal2 " "Info: Found entity 1: signal2" {  } { { "signal2.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal2.vhdl" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal3.vhdl 2 1 " "Info: Found 2 design units, including 1 entities, in source file signal3.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 signal3-a " "Info: Found design unit 1: signal3-a" {  } { { "signal3.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal3.vhdl" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 signal3 " "Info: Found entity 1: signal3" {  } { { "signal3.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal3.vhdl" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal4.vhdl 2 1 " "Info: Found 2 design units, including 1 entities, in source file signal4.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 signal4-a " "Info: Found design unit 1: signal4-a" {  } { { "signal4.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal4.vhdl" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 signal4 " "Info: Found entity 1: signal4" {  } { { "signal4.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal4.vhdl" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "signal.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file signal.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 signal " "Info: Found entity 1: signal" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "signal " "Info: Elaborating entity \"signal\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "selectsignal selectsignal:inst7 " "Info: Elaborating entity \"selectsignal\" for hierarchy \"selectsignal:inst7\"" {  } { { "signal.bdf" "inst7" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 32 344 472 304 "inst7" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s1 selectsignal.vhd(14) " "Warning: VHDL Process Statement warning at selectsignal.vhd(14): signal \"s1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s2 selectsignal.vhd(15) " "Warning: VHDL Process Statement warning at selectsignal.vhd(15): signal \"s2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s3 selectsignal.vhd(16) " "Warning: VHDL Process Statement warning at selectsignal.vhd(16): signal \"s3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s4 selectsignal.vhd(17) " "Warning: VHDL Process Statement warning at selectsignal.vhd(17): signal \"s4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "s5 selectsignal.vhd(18) " "Warning: VHDL Process Statement warning at selectsignal.vhd(18): signal \"s5\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "q selectsignal.vhd(11) " "Warning: VHDL Process Statement warning at selectsignal.vhd(11): signal or variable \"q\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"q\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 11 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "signal1 signal1:inst " "Info: Elaborating entity \"signal1\" for hierarchy \"signal1:inst\"" {  } { { "signal.bdf" "inst" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 32 96 224 112 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "signal2 signal2:inst1 " "Info: Elaborating entity \"signal2\" for hierarchy \"signal2:inst1\"" {  } { { "signal.bdf" "inst1" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 120 96 224 200 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "signal3 signal3:inst2 " "Info: Elaborating entity \"signal3\" for hierarchy \"signal3:inst2\"" {  } { { "signal.bdf" "inst2" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 208 96 224 288 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "signal4 signal4:inst3 " "Info: Elaborating entity \"signal4\" for hierarchy \"signal4:inst3\"" {  } { { "signal.bdf" "inst3" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 296 96 224 376 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "signal5.vhd 2 1 " "Info: Using design file signal5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 signal5-a " "Info: Found design unit 1: signal5-a" {  } { { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 signal5 " "Info: Found entity 1: signal5" {  } { { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "signal5 signal5:inst10 " "Info: Elaborating entity \"signal5\" for hierarchy \"signal5:inst10\"" {  } { { "signal.bdf" "inst10" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 408 96 224 488 "inst10" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "signal5.vhd(47) " "Info: VHDL Case Statement information at signal5.vhd(47): OTHERS choice is never selected" {  } { { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 47 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "signal4:inst3\|tmp\[3\] data_in GND " "Warning: Reduced register \"signal4:inst3\|tmp\[3\]\" with stuck data_in port to stuck value GND" {  } { { "signal4.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal4.vhdl" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "signal4:inst3\|tmp\[2\] data_in GND " "Warning: Reduced register \"signal4:inst3\|tmp\[2\]\" with stuck data_in port to stuck value GND" {  } { { "signal4.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal4.vhdl" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "signal4:inst3\|tmp\[1\] data_in GND " "Warning: Reduced register \"signal4:inst3\|tmp\[1\]\" with stuck data_in port to stuck value GND" {  } { { "signal4.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal4.vhdl" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "signal4:inst3\|tmp\[0\] data_in GND " "Warning: Reduced register \"signal4:inst3\|tmp\[0\]\" with stuck data_in port to stuck value GND" {  } { { "signal4.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal4.vhdl" 11 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "signal2:inst1\|tmp\[0\] signal4:inst3\|tmp\[4\] " "Info: Duplicate register \"signal2:inst1\|tmp\[0\]\" merged to single register \"signal4:inst3\|tmp\[4\]\"" {  } { { "signal2.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal2.vhdl" 11 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[7\] " "Warning: Latch selectsignal:inst7\|q\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[2\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[6\] " "Warning: Latch selectsignal:inst7\|q\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[5\] " "Warning: Latch selectsignal:inst7\|q\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[4\] " "Warning: Latch selectsignal:inst7\|q\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[3\] " "Warning: Latch selectsignal:inst7\|q\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[2\] " "Warning: Latch selectsignal:inst7\|q\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[1\] " "Warning: Latch selectsignal:inst7\|q\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "selectsignal:inst7\|q\[0\] " "Warning: Latch selectsignal:inst7\|q\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA sel\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal sel\[1\]" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "127 " "Info: Implemented 127 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "114 " "Info: Implemented 114 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 07 22:46:49 2006 " "Info: Processing ended: Tue Mar 07 22:46:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}