signal.hier_info

一个简单的多种信号的发生器 包括正玄

|signal
q[0] <= selectsignal:inst7.q[0]
q[1] <= selectsignal:inst7.q[1]
q[2] <= selectsignal:inst7.q[2]
q[3] <= selectsignal:inst7.q[3]
q[4] <= selectsignal:inst7.q[4]
q[5] <= selectsignal:inst7.q[5]
q[6] <= selectsignal:inst7.q[6]
q[7] <= selectsignal:inst7.q[7]
clk => signal1:inst.clk
clk => signal2:inst1.clk
clk => signal3:inst2.clk
clk => signal4:inst3.clk
clk => signal5:inst10.clk
reset => signal1:inst.reset
reset => signal2:inst1.reset
reset => signal3:inst2.reset
reset => signal4:inst3.reset
reset => signal5:inst10.reset
sel[0] => selectsignal:inst7.sel[0]
sel[1] => selectsignal:inst7.sel[1]
sel[2] => selectsignal:inst7.sel[2]


|signal|selectsignal:inst7
sel[0] => Mux~0.IN2
sel[0] => Mux~1.IN10
sel[0] => Mux~2.IN2
sel[0] => Mux~3.IN10
sel[0] => Mux~4.IN2
sel[0] => Mux~5.IN2
sel[0] => Mux~6.IN2
sel[0] => Mux~7.IN2
sel[0] => Mux~8.IN2
sel[0] => Mux~9.IN2
sel[1] => Mux~0.IN1
sel[1] => Mux~1.IN9
sel[1] => Mux~2.IN1
sel[1] => Mux~3.IN9
sel[1] => Mux~4.IN1
sel[1] => Mux~5.IN1
sel[1] => Mux~6.IN1
sel[1] => Mux~7.IN1
sel[1] => Mux~8.IN1
sel[1] => Mux~9.IN1
sel[2] => Mux~0.IN0
sel[2] => Mux~1.IN8
sel[2] => Mux~2.IN0
sel[2] => Mux~3.IN8
sel[2] => Mux~4.IN0
sel[2] => Mux~5.IN0
sel[2] => Mux~6.IN0
sel[2] => Mux~7.IN0
sel[2] => Mux~8.IN0
sel[2] => Mux~9.IN0
s1[0] => Mux~9.IN3
s1[1] => Mux~8.IN3
s1[2] => Mux~7.IN3
s1[3] => Mux~6.IN3
s1[4] => Mux~5.IN3
s1[5] => Mux~4.IN3
s1[6] => Mux~2.IN3
s1[7] => Mux~0.IN3
s2[0] => Mux~9.IN4
s2[1] => Mux~8.IN4
s2[2] => Mux~7.IN4
s2[3] => Mux~6.IN4
s2[4] => Mux~5.IN4
s2[5] => Mux~4.IN4
s2[6] => Mux~2.IN4
s2[7] => Mux~0.IN4
s3[0] => Mux~9.IN5
s3[1] => Mux~8.IN5
s3[2] => Mux~7.IN5
s3[3] => Mux~6.IN5
s3[4] => Mux~5.IN5
s3[5] => Mux~4.IN5
s3[6] => Mux~2.IN5
s3[7] => Mux~0.IN5
s4[0] => Mux~9.IN6
s4[1] => Mux~8.IN6
s4[2] => Mux~7.IN6
s4[3] => Mux~6.IN6
s4[4] => Mux~5.IN6
s4[5] => Mux~4.IN6
s4[6] => Mux~2.IN6
s4[7] => Mux~0.IN6
s5[0] => Mux~9.IN7
s5[1] => Mux~8.IN7
s5[2] => Mux~7.IN7
s5[3] => Mux~6.IN7
s5[4] => Mux~5.IN7
s5[5] => Mux~4.IN7
s5[6] => Mux~2.IN7
s5[7] => Mux~0.IN7
q[0] <= q[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]$latch.DB_MAX_OUTPUT_PORT_TYPE


|signal|signal1:inst
clk => tmp[6].CLK
clk => tmp[5].CLK
clk => tmp[4].CLK
clk => tmp[3].CLK
clk => tmp[2].CLK
clk => tmp[1].CLK
clk => tmp[0].CLK
clk => a.CLK
clk => tmp[7].CLK
reset => tmp[6].ACLR
reset => tmp[5].ACLR
reset => tmp[4].ACLR
reset => tmp[3].ACLR
reset => tmp[2].ACLR
reset => tmp[1].ACLR
reset => tmp[0].ACLR
reset => tmp[7].ACLR
reset => a.ENA
q[0] <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= tmp[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= tmp[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= tmp[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= tmp[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= tmp[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= tmp[7].DB_MAX_OUTPUT_PORT_TYPE


|signal|signal2:inst1
clk => tmp[6].CLK
clk => tmp[5].CLK
clk => tmp[4].CLK
clk => tmp[3].CLK
clk => tmp[2].CLK
clk => tmp[1].CLK
clk => tmp[0].CLK
clk => tmp[7].CLK
reset => tmp[6].ACLR
reset => tmp[5].ACLR
reset => tmp[4].ACLR
reset => tmp[3].ACLR
reset => tmp[2].ACLR
reset => tmp[1].ACLR
reset => tmp[0].ACLR
reset => tmp[7].ACLR
q[0] <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= tmp[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= tmp[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= tmp[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= tmp[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= tmp[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= tmp[7].DB_MAX_OUTPUT_PORT_TYPE


|signal|signal3:inst2
clk => tmp[6].CLK
clk => tmp[5].CLK
clk => tmp[4].CLK
clk => tmp[3].CLK
clk => tmp[2].CLK
clk => tmp[1].CLK
clk => tmp[0].CLK
clk => tmp[7].CLK
reset => tmp[6].PRESET
reset => tmp[5].PRESET
reset => tmp[4].PRESET
reset => tmp[3].PRESET
reset => tmp[2].PRESET
reset => tmp[1].PRESET
reset => tmp[0].PRESET
reset => tmp[7].PRESET
q[0] <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= tmp[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= tmp[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= tmp[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= tmp[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= tmp[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= tmp[7].DB_MAX_OUTPUT_PORT_TYPE


|signal|signal4:inst3
clk => tmp[6].CLK
clk => tmp[5].CLK
clk => tmp[4].CLK
clk => tmp[3].CLK
clk => tmp[2].CLK
clk => tmp[1].CLK
clk => tmp[0].CLK
clk => tmp[7].CLK
reset => tmp[6].ACLR
reset => tmp[5].ACLR
reset => tmp[4].ACLR
reset => tmp[3].ACLR
reset => tmp[2].ACLR
reset => tmp[1].ACLR
reset => tmp[0].ACLR
reset => tmp[7].ACLR
q[0] <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= tmp[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= tmp[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= tmp[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= tmp[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= tmp[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= tmp[7].DB_MAX_OUTPUT_PORT_TYPE


|signal|signal5:inst10
clk => q[4].CLK
clk => q[3].CLK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
clk => q[5].CLK
reset => ~NO_FANOUT~
display[0] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
display[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE