signal.tan.qmsg

一个简单的多种信号的发生器 包括正玄

{ "Info" "ITDB_FULL_TPD_RESULT" "sel\[0\] q\[5\] 15.061 ns Longest " "Info: Longest tpd from source pin \"sel\[0\]\" to destination pin \"q\[5\]\" is 15.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[0\] 1 PIN PIN_96 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_96; Fanout = 8; PIN Node = 'sel\[0\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { sel[0] } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 16 -256 -88 32 "sel\[2..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.436 ns) + CELL(0.511 ns) 5.079 ns selectsignal:inst7\|Mux~522 2 COMB LC_X4_Y3_N6 8 " "Info: 2: + IC(3.436 ns) + CELL(0.511 ns) = 5.079 ns; Loc. = LC_X4_Y3_N6; Fanout = 8; COMB Node = 'selectsignal:inst7\|Mux~522'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.947 ns" { sel[0] selectsignal:inst7|Mux~522 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.981 ns) + CELL(0.511 ns) 7.571 ns selectsignal:inst7\|Mux~526 3 COMB LC_X4_Y2_N1 1 " "Info: 3: + IC(1.981 ns) + CELL(0.511 ns) = 7.571 ns; Loc. = LC_X4_Y2_N1; Fanout = 1; COMB Node = 'selectsignal:inst7\|Mux~526'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.492 ns" { selectsignal:inst7|Mux~522 selectsignal:inst7|Mux~526 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 8.076 ns selectsignal:inst7\|Mux~527 4 COMB LC_X4_Y2_N2 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 8.076 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'selectsignal:inst7\|Mux~527'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "0.505 ns" { selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.200 ns) 9.001 ns selectsignal:inst7\|Mux~528 5 COMB LC_X4_Y2_N5 2 " "Info: 5: + IC(0.725 ns) + CELL(0.200 ns) = 9.001 ns; Loc. = LC_X4_Y2_N5; Fanout = 2; COMB Node = 'selectsignal:inst7\|Mux~528'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "0.925 ns" { selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.882 ns) 10.883 ns selectsignal:inst7\|q\[5\] 6 COMB LOOP LC_X3_Y2_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(1.882 ns) = 10.883 ns; Loc. = LC_X3_Y2_N2; Fanout = 2; COMB LOOP Node = 'selectsignal:inst7\|q\[5\]'" { { "Info" "ITDB_PART_OF_SCC" "selectsignal:inst7\|q\[5\] LC_X3_Y2_N2 " "Info: Loc. = LC_X3_Y2_N2; Node \"selectsignal:inst7\|q\[5\]\"" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { selectsignal:inst7|q[5] } "NODE_NAME" } "" } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { selectsignal:inst7|q[5] } "NODE_NAME" } "" } } { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "1.882 ns" { selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] } "NODE_NAME" } "" } } { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.856 ns) + CELL(2.322 ns) 15.061 ns q\[5\] 7 PIN PIN_37 0 " "Info: 7: + IC(1.856 ns) + CELL(2.322 ns) = 15.061 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'q\[5\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "4.178 ns" { selectsignal:inst7|q[5] q[5] } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 160 536 712 176 "q\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.758 ns 44.87 % " "Info: Total cell delay = 6.758 ns ( 44.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.303 ns 55.13 % " "Info: Total interconnect delay = 8.303 ns ( 55.13 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "15.061 ns" { sel[0] selectsignal:inst7|Mux~522 selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] q[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "15.061 ns" { sel[0] sel[0]~combout selectsignal:inst7|Mux~522 selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] q[5] } { 0.000ns 0.000ns 3.436ns 1.981ns 0.305ns 0.725ns 0.000ns 1.856ns } { 0.000ns 1.132ns 0.511ns 0.511ns 0.200ns 0.200ns 1.882ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "signal1:inst\|a reset clk -2.496 ns register " "Info: th for register \"signal1:inst\|a\" (data pin = \"reset\", clock pin = \"clk\") is -2.496 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.841 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.841 ns signal1:inst\|a 2 REG LC_X2_Y3_N3 25 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst\|a'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.185 ns" { clk signal1:inst|a } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.574 ns 67.01 % " "Info: Total cell delay = 2.574 ns ( 67.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns 32.99 % " "Info: Total interconnect delay = 1.267 ns ( 32.99 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|a } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.558 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns reset 1 PIN PIN_12 28 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_12; Fanout = 28; PIN Node = 'reset'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { reset } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 64 -256 -88 80 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.659 ns) + CELL(1.243 ns) 6.558 ns signal1:inst\|a 2 REG LC_X2_Y3_N3 25 " "Info: 2: + IC(3.659 ns) + CELL(1.243 ns) = 6.558 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst\|a'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "4.902 ns" { reset signal1:inst|a } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.899 ns 44.21 % " "Info: Total cell delay = 2.899 ns ( 44.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.659 ns 55.79 % " "Info: Total interconnect delay = 3.659 ns ( 55.79 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "6.558 ns" { reset signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "6.558 ns" { reset reset~combout signal1:inst|a } { 0.000ns 0.000ns 3.659ns } { 0.000ns 1.656ns 1.243ns } } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|a } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "6.558 ns" { reset signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "6.558 ns" { reset reset~combout signal1:inst|a } { 0.000ns 0.000ns 3.659ns } { 0.000ns 1.656ns 1.243ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 07 22:47:00 2006 " "Info: Processing ended: Tue Mar 07 22:47:00 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}