signal.tan.qmsg

一个简单的多种信号的发生器 包括正玄

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "selectsignal:inst7\|q\[6\] " "Info: Node \"selectsignal:inst7\|q\[6\]\"" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "selectsignal:inst7\|q\[7\] " "Info: Node \"selectsignal:inst7\|q\[7\]\"" {  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}  } { { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } } { "d:/quartus5/bin/Assignment Editor.qase" "" { Assignment "d:/quartus5/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register signal1:inst\|tmp\[6\] register signal1:inst\|tmp\[5\] 119.85 MHz 8.344 ns Internal " "Info: Clock \"clk\" has Internal fmax of 119.85 MHz between source register \"signal1:inst\|tmp\[6\]\" and destination register \"signal1:inst\|tmp\[5\]\" (period= 8.344 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.635 ns + Longest register register " "Info: + Longest register to register delay is 7.635 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns signal1:inst\|tmp\[6\] 1 REG LC_X3_Y3_N6 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N6; Fanout = 6; REG Node = 'signal1:inst\|tmp\[6\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { signal1:inst|tmp[6] } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.481 ns) + CELL(0.200 ns) 2.681 ns signal1:inst\|reduce_nor~87 2 COMB LC_X5_Y3_N9 1 " "Info: 2: + IC(2.481 ns) + CELL(0.200 ns) = 2.681 ns; Loc. = LC_X5_Y3_N9; Fanout = 1; COMB Node = 'signal1:inst\|reduce_nor~87'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.681 ns" { signal1:inst|tmp[6] signal1:inst|reduce_nor~87 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.200 ns) 4.562 ns signal1:inst\|reduce_nor~1 3 COMB LC_X3_Y3_N8 2 " "Info: 3: + IC(1.681 ns) + CELL(0.200 ns) = 4.562 ns; Loc. = LC_X3_Y3_N8; Fanout = 2; COMB Node = 'signal1:inst\|reduce_nor~1'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "1.881 ns" { signal1:inst|reduce_nor~87 signal1:inst|reduce_nor~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.067 ns signal1:inst\|tmp\[2\]~390 4 COMB LC_X3_Y3_N9 8 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.067 ns; Loc. = LC_X3_Y3_N9; Fanout = 8; COMB Node = 'signal1:inst\|tmp\[2\]~390'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "0.505 ns" { signal1:inst|reduce_nor~1 signal1:inst|tmp[2]~390 } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.660 ns) + CELL(1.908 ns) 7.635 ns signal1:inst\|tmp\[5\] 5 REG LC_X3_Y3_N5 6 " "Info: 5: + IC(0.660 ns) + CELL(1.908 ns) = 7.635 ns; Loc. = LC_X3_Y3_N5; Fanout = 6; REG Node = 'signal1:inst\|tmp\[5\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.568 ns" { signal1:inst|tmp[2]~390 signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.508 ns 32.85 % " "Info: Total cell delay = 2.508 ns ( 32.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.127 ns 67.15 % " "Info: Total interconnect delay = 5.127 ns ( 67.15 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "7.635 ns" { signal1:inst|tmp[6] signal1:inst|reduce_nor~87 signal1:inst|reduce_nor~1 signal1:inst|tmp[2]~390 signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "7.635 ns" { signal1:inst|tmp[6] signal1:inst|reduce_nor~87 signal1:inst|reduce_nor~1 signal1:inst|tmp[2]~390 signal1:inst|tmp[5] } { 0.000ns 2.481ns 1.681ns 0.305ns 0.660ns } { 0.000ns 0.200ns 0.200ns 0.200ns 1.908ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.841 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.841 ns signal1:inst\|tmp\[5\] 2 REG LC_X3_Y3_N5 6 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X3_Y3_N5; Fanout = 6; REG Node = 'signal1:inst\|tmp\[5\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.185 ns" { clk signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.574 ns 67.01 % " "Info: Total cell delay = 2.574 ns ( 67.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns 32.99 % " "Info: Total interconnect delay = 1.267 ns ( 32.99 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|tmp[5] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.841 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.841 ns signal1:inst\|tmp\[6\] 2 REG LC_X3_Y3_N6 6 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X3_Y3_N6; Fanout = 6; REG Node = 'signal1:inst\|tmp\[6\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.185 ns" { clk signal1:inst|tmp[6] } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.574 ns 67.01 % " "Info: Total cell delay = 2.574 ns ( 67.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns 32.99 % " "Info: Total interconnect delay = 1.267 ns ( 32.99 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|tmp[6] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|tmp[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|tmp[5] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|tmp[6] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|tmp[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 11 -1 0 } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "7.635 ns" { signal1:inst|tmp[6] signal1:inst|reduce_nor~87 signal1:inst|reduce_nor~1 signal1:inst|tmp[2]~390 signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "7.635 ns" { signal1:inst|tmp[6] signal1:inst|reduce_nor~87 signal1:inst|reduce_nor~1 signal1:inst|tmp[2]~390 signal1:inst|tmp[5] } { 0.000ns 2.481ns 1.681ns 0.305ns 0.660ns } { 0.000ns 0.200ns 0.200ns 0.200ns 1.908ns } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|tmp[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|tmp[5] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|tmp[6] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|tmp[6] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "signal1:inst\|a reset clk 3.050 ns register " "Info: tsu for register \"signal1:inst\|a\" (data pin = \"reset\", clock pin = \"clk\") is 3.050 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.558 ns + Longest pin register " "Info: + Longest pin to register delay is 6.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns reset 1 PIN PIN_12 28 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_12; Fanout = 28; PIN Node = 'reset'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { reset } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 64 -256 -88 80 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.659 ns) + CELL(1.243 ns) 6.558 ns signal1:inst\|a 2 REG LC_X2_Y3_N3 25 " "Info: 2: + IC(3.659 ns) + CELL(1.243 ns) = 6.558 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst\|a'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "4.902 ns" { reset signal1:inst|a } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.899 ns 44.21 % " "Info: Total cell delay = 2.899 ns ( 44.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.659 ns 55.79 % " "Info: Total interconnect delay = 3.659 ns ( 55.79 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "6.558 ns" { reset signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "6.558 ns" { reset reset~combout signal1:inst|a } { 0.000ns 0.000ns 3.659ns } { 0.000ns 1.656ns 1.243ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.841 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.841 ns signal1:inst\|a 2 REG LC_X2_Y3_N3 25 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst\|a'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.185 ns" { clk signal1:inst|a } "NODE_NAME" } "" } } { "signal1.vhdl" "" { Text "F:/myproject/信号发生器/signal/signal1.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.574 ns 67.01 % " "Info: Total cell delay = 2.574 ns ( 67.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns 32.99 % " "Info: Total interconnect delay = 1.267 ns ( 32.99 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|a } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "6.558 ns" { reset signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "6.558 ns" { reset reset~combout signal1:inst|a } { 0.000ns 0.000ns 3.659ns } { 0.000ns 1.656ns 1.243ns } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal1:inst|a } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal1:inst|a } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[5\] signal5:inst10\|q\[3\] 17.165 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[5\]\" through register \"signal5:inst10\|q\[3\]\" is 17.165 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.841 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.656 ns) 1.656 ns clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { clk } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 40 -256 -88 56 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.841 ns signal5:inst10\|q\[3\] 2 REG LC_X5_Y2_N4 25 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X5_Y2_N4; Fanout = 25; REG Node = 'signal5:inst10\|q\[3\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "2.185 ns" { clk signal5:inst10|q[3] } "NODE_NAME" } "" } } { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.574 ns 67.01 % " "Info: Total cell delay = 2.574 ns ( 67.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns 32.99 % " "Info: Total interconnect delay = 1.267 ns ( 32.99 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal5:inst10|q[3] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal5:inst10|q[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.948 ns + Longest register pin " "Info: + Longest register to pin delay is 12.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns signal5:inst10\|q\[3\] 1 REG LC_X5_Y2_N4 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N4; Fanout = 25; REG Node = 'signal5:inst10\|q\[3\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { signal5:inst10|q[3] } "NODE_NAME" } "" } } { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.914 ns) 1.926 ns signal5:inst10\|display\[5\]~1079 2 COMB LC_X5_Y2_N0 2 " "Info: 2: + IC(1.012 ns) + CELL(0.914 ns) = 1.926 ns; Loc. = LC_X5_Y2_N0; Fanout = 2; COMB Node = 'signal5:inst10\|display\[5\]~1079'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "1.926 ns" { signal5:inst10|q[3] signal5:inst10|display[5]~1079 } "NODE_NAME" } "" } } { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.248 ns) + CELL(0.511 ns) 3.685 ns signal5:inst10\|display\[5\]~1082 3 COMB LC_X4_Y2_N4 1 " "Info: 3: + IC(1.248 ns) + CELL(0.511 ns) = 3.685 ns; Loc. = LC_X4_Y2_N4; Fanout = 1; COMB Node = 'signal5:inst10\|display\[5\]~1082'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "1.759 ns" { signal5:inst10|display[5]~1079 signal5:inst10|display[5]~1082 } "NODE_NAME" } "" } } { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.511 ns) 4.953 ns signal5:inst10\|display\[5\]~1083 4 COMB LC_X4_Y2_N0 1 " "Info: 4: + IC(0.757 ns) + CELL(0.511 ns) = 4.953 ns; Loc. = LC_X4_Y2_N0; Fanout = 1; COMB Node = 'signal5:inst10\|display\[5\]~1083'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "1.268 ns" { signal5:inst10|display[5]~1082 signal5:inst10|display[5]~1083 } "NODE_NAME" } "" } } { "signal5.vhd" "" { Text "F:/myproject/信号发生器/signal/signal5.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.458 ns selectsignal:inst7\|Mux~526 5 COMB LC_X4_Y2_N1 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.458 ns; Loc. = LC_X4_Y2_N1; Fanout = 1; COMB Node = 'selectsignal:inst7\|Mux~526'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "0.505 ns" { signal5:inst10|display[5]~1083 selectsignal:inst7|Mux~526 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.963 ns selectsignal:inst7\|Mux~527 6 COMB LC_X4_Y2_N2 1 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 5.963 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'selectsignal:inst7\|Mux~527'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "0.505 ns" { selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.200 ns) 6.888 ns selectsignal:inst7\|Mux~528 7 COMB LC_X4_Y2_N5 2 " "Info: 7: + IC(0.725 ns) + CELL(0.200 ns) = 6.888 ns; Loc. = LC_X4_Y2_N5; Fanout = 2; COMB Node = 'selectsignal:inst7\|Mux~528'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "0.925 ns" { selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.882 ns) 8.770 ns selectsignal:inst7\|q\[5\] 8 COMB LOOP LC_X3_Y2_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(1.882 ns) = 8.770 ns; Loc. = LC_X3_Y2_N2; Fanout = 2; COMB LOOP Node = 'selectsignal:inst7\|q\[5\]'" { { "Info" "ITDB_PART_OF_SCC" "selectsignal:inst7\|q\[5\] LC_X3_Y2_N2 " "Info: Loc. = LC_X3_Y2_N2; Node \"selectsignal:inst7\|q\[5\]\"" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { selectsignal:inst7|q[5] } "NODE_NAME" } "" } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "" { selectsignal:inst7|q[5] } "NODE_NAME" } "" } } { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "1.882 ns" { selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] } "NODE_NAME" } "" } } { "selectsignal.vhd" "" { Text "F:/myproject/信号发生器/signal/selectsignal.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.856 ns) + CELL(2.322 ns) 12.948 ns q\[5\] 9 PIN PIN_37 0 " "Info: 9: + IC(1.856 ns) + CELL(2.322 ns) = 12.948 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'q\[5\]'" {  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "4.178 ns" { selectsignal:inst7|q[5] q[5] } "NODE_NAME" } "" } } { "signal.bdf" "" { Schematic "F:/myproject/信号发生器/signal/signal.bdf" { { 160 536 712 176 "q\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.740 ns 52.05 % " "Info: Total cell delay = 6.740 ns ( 52.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.208 ns 47.95 % " "Info: Total interconnect delay = 6.208 ns ( 47.95 % )" {  } {  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "12.948 ns" { signal5:inst10|q[3] signal5:inst10|display[5]~1079 signal5:inst10|display[5]~1082 signal5:inst10|display[5]~1083 selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] q[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "12.948 ns" { signal5:inst10|q[3] signal5:inst10|display[5]~1079 signal5:inst10|display[5]~1082 signal5:inst10|display[5]~1083 selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] q[5] } { 0.000ns 1.012ns 1.248ns 0.757ns 0.305ns 0.305ns 0.725ns 0.000ns 1.856ns } { 0.000ns 0.914ns 0.511ns 0.511ns 0.200ns 0.200ns 0.200ns 1.882ns 2.322ns } } }  } 0}  } { { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "3.841 ns" { clk signal5:inst10|q[3] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "3.841 ns" { clk clk~combout signal5:inst10|q[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.656ns 0.918ns } } } { "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" "" { Report "F:/myproject/信号发生器/signal/db/signal_cmp.qrpt" Compiler "signal" "UNKNOWN" "V1" "F:/myproject/信号发生器/signal/db/signal.quartus_db" { Floorplan "F:/myproject/信号发生器/signal/" "" "12.948 ns" { signal5:inst10|q[3] signal5:inst10|display[5]~1079 signal5:inst10|display[5]~1082 signal5:inst10|display[5]~1083 selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] q[5] } "NODE_NAME" } "" } } { "d:/quartus5/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus5/bin/Technology_Viewer.qrui" "12.948 ns" { signal5:inst10|q[3] signal5:inst10|display[5]~1079 signal5:inst10|display[5]~1082 signal5:inst10|display[5]~1083 selectsignal:inst7|Mux~526 selectsignal:inst7|Mux~527 selectsignal:inst7|Mux~528 selectsignal:inst7|q[5] q[5] } { 0.000ns 1.012ns 1.248ns 0.757ns 0.305ns 0.305ns 0.725ns 0.000ns 1.856ns } { 0.000ns 0.914ns 0.511ns 0.511ns 0.200ns 0.200ns 0.200ns 1.882ns 2.322ns } } }  } 0}