signal.map.rpt

一个简单的多种信号的发生器 包括正玄

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                             ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name        ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------+
; |signal                    ; 114 (0)     ; 34           ; 0          ; 13   ; 0            ; 80 (0)       ; 4 (0)             ; 30 (0)           ; 30 (0)          ; |signal                    ;
;    |selectsignal:inst7|    ; 32 (32)     ; 0            ; 0          ; 0    ; 0            ; 32 (32)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |signal|selectsignal:inst7 ;
;    |signal1:inst|          ; 17 (17)     ; 9            ; 0          ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |signal|signal1:inst       ;
;    |signal2:inst1|         ; 7 (7)       ; 7            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; 7 (7)           ; |signal|signal2:inst1      ;
;    |signal3:inst2|         ; 8 (8)       ; 8            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |signal|signal3:inst2      ;
;    |signal4:inst3|         ; 6 (6)       ; 4            ; 0          ; 0    ; 0            ; 2 (2)        ; 4 (4)             ; 0 (0)            ; 0 (0)           ; |signal|signal4:inst3      ;
;    |signal5:inst10|        ; 44 (44)     ; 6            ; 0          ; 0    ; 0            ; 38 (38)      ; 0 (0)             ; 6 (6)            ; 6 (6)           ; |signal|signal5:inst10     ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; selectsignal:inst7|q[7]                       ;   ;
; selectsignal:inst7|q[6]                       ;   ;
; selectsignal:inst7|q[5]                       ;   ;
; selectsignal:inst7|q[4]                       ;   ;
; selectsignal:inst7|q[3]                       ;   ;
; selectsignal:inst7|q[2]                       ;   ;
; selectsignal:inst7|q[1]                       ;   ;
; selectsignal:inst7|q[0]                       ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 34    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 19    ;
; Number of registers using Asynchronous Load  ; 8     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |signal|signal1:inst|tmp[2]      ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; No         ; |signal|selectsignal:inst7|Mux~6 ;
; 5:1                ; 3 bits    ; 9 LEs         ; 9 LEs                ; 0 LEs                  ; No         ; |signal|selectsignal:inst7|Mux~2 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/myproject/信号发生器/signal/signal.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Mar 07 22:46:43 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off signal -c signal
Info: Found 2 design units, including 1 entities, in source file selectsignal.vhd
    Info: Found design unit 1: selectsignal-a
    Info: Found entity 1: selectsignal
Info: Found 2 design units, including 1 entities, in source file signal1.vhdl
    Info: Found design unit 1: signal1-a
    Info: Found entity 1: signal1
Info: Found 2 design units, including 1 entities, in source file signal2.vhdl
    Info: Found design unit 1: signal2-a
    Info: Found entity 1: signal2
Info: Found 2 design units, including 1 entities, in source file signal3.vhdl
    Info: Found design unit 1: signal3-a
    Info: Found entity 1: signal3
Info: Found 2 design units, including 1 entities, in source file signal4.vhdl
    Info: Found design unit 1: signal4-a
    Info: Found entity 1: signal4
Info: Found 1 design units, including 1 entities, in source file signal.bdf
    Info: Found entity 1: signal
Info: Elaborating entity "signal" for the top level hierarchy
Info: Elaborating entity "selectsignal" for hierarchy "selectsignal:inst7"
Warning: VHDL Process Statement warning at selectsignal.vhd(14): signal "s1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at selectsignal.vhd(15): signal "s2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at selectsignal.vhd(16): signal "s3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at selectsignal.vhd(17): signal "s4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at selectsignal.vhd(18): signal "s5" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at selectsignal.vhd(11): signal or variable "q" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "q" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "signal1" for hierarchy "signal1:inst"
Info: Elaborating entity "signal2" for hierarchy "signal2:inst1"
Info: Elaborating entity "signal3" for hierarchy "signal3:inst2"
Info: Elaborating entity "signal4" for hierarchy "signal4:inst3"
Info: Using design file signal5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: signal5-a
    Info: Found entity 1: signal5
Info: Elaborating entity "signal5" for hierarchy "signal5:inst10"
Info: VHDL Case Statement information at signal5.vhd(47): OTHERS choice is never selected
Warning: Reduced register "signal4:inst3|tmp[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "signal4:inst3|tmp[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "signal4:inst3|tmp[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "signal4:inst3|tmp[0]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "signal2:inst1|tmp[0]" merged to single register "signal4:inst3|tmp[4]"
Warning: Latch selectsignal:inst7|q[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[2]
Warning: Latch selectsignal:inst7|q[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Warning: Latch selectsignal:inst7|q[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Warning: Latch selectsignal:inst7|q[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Warning: Latch selectsignal:inst7|q[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Warning: Latch selectsignal:inst7|q[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Warning: Latch selectsignal:inst7|q[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Warning: Latch selectsignal:inst7|q[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal sel[1]
Info: Implemented 127 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 8 output pins
    Info: Implemented 114 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings
    Info: Processing ended: Tue Mar 07 22:46:49 2006
    Info: Elapsed time: 00:00:06