signal5.vhd

一个简单的多种信号的发生器 包括正玄

library ieee;
use ieee.std_logic_1164.all;

entity signal5 is
   port(
          clk,reset: in std_logic;
          display: out integer range 255 downto 0
       );
end;

architecture a of signal5 is
    signal q: integer range 63 downto 0;
    signal d: integer range 255 downto 0;
    begin 
      process(clk)
      begin 
       if(clk'event and clk='1')then
          q<=q+1;
       end if;
      end process;
      process(q)
      begin
         case q is
       when 00=>d<=255;when 01=>d<=254;when 02=>d<=252;
       when 03=>d<=249;when 04=>d<=245;when 05=>d<=239;

       when 06=>d<=233;when 07=>d<=225;when 08=>d<=217;
       when 09=>d<=207;when 10=>d<=197;when 11=>d<=186;
       when 12=>d<=174;when 13=>d<=162;when 14=>d<=150;
       when 15=>d<=137;when 16=>d<=124;when 17=>d<=112;
       when 18=>d<=99;when 19=>d<=87;when 20=>d<=75;
       when 21=>d<=64;when 22=>d<=53;when 23=>d<=43;

       when 24=>d<=34;when 25=>d<=26;when 26=>d<=19;
       when 27=>d<=13;when 28=>d<=8;when 29=>d<=4;
       when 30=>d<=1;when 31=>d<=0;when 32=>d<=0;
       when 33=>d<=1;when 34=>d<=4;when 35=>d<=8;
       when 36=>d<=13;when 37=>d<=19;when 38=>d<=26;
       when 39=>d<=34;when 40=>d<=43;when 41=>d<=53;
       when 42=>d<=64;when 43=>d<=75;when 44=>d<=87;
       when 45=>d<=99;when 46=>d<=112;when 47=>d<=124;
       when 48=>d<=137;when 49=>d<=150;when 50=>d<=162;
       when 51=>d<=174;when 52=>d<=186;when 53=>d<=197;
       when 54=>d<=207;when 55=>d<=217;when 56=>d<=225;
       when 57=>d<=233;when 58=>d<=239;when 59=>d<=245;
       when 60=>d<=249;when 61=>d<=252;when 62=>d<=254;
       when 63=>d<=255;when others=>null;
      end case;
     end process;
  display<=d;
end a;