selectsignal.vhd

来自「一个简单的多种信号的发生器 包括正玄」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity selectsignal is
  port( sel:in std_logic_vector(2 downto 0);
        s1,s2,s3,s4,s5: in std_logic_vector(7 downto 0);
        q:out std_logic_vector(7 downto 0));
end selectsignal;
architecture a of selectsignal is
begin
process(sel)
begin
case sel is
     when "000"=>q<=s1;
     when "001"=>q<=s2;
     when "010"=>q<=s3;
     when "011"=>q<=s4;
     when "100"=>q<=s5;
     when others=>null;
end case;
end process;
end a;