signal.tan.rpt

一个简单的多种信号的发生器 包括正玄

Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off signal -c signal
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "selectsignal:inst7|q[7]" is a latch
    Warning: Node "selectsignal:inst7|q[6]" is a latch
    Warning: Node "selectsignal:inst7|q[5]" is a latch
    Warning: Node "selectsignal:inst7|q[4]" is a latch
    Warning: Node "selectsignal:inst7|q[3]" is a latch
    Warning: Node "selectsignal:inst7|q[2]" is a latch
    Warning: Node "selectsignal:inst7|q[1]" is a latch
    Warning: Node "selectsignal:inst7|q[0]" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[0]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[1]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[2]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[3]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[4]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[5]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[6]"
Info: Found combinational loop of 1 nodes
    Info: Node "selectsignal:inst7|q[7]"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 119.85 MHz between source register "signal1:inst|tmp[6]" and destination register "signal1:inst|tmp[5]" (period= 8.344 ns)
    Info: + Longest register to register delay is 7.635 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N6; Fanout = 6; REG Node = 'signal1:inst|tmp[6]'
        Info: 2: + IC(2.481 ns) + CELL(0.200 ns) = 2.681 ns; Loc. = LC_X5_Y3_N9; Fanout = 1; COMB Node = 'signal1:inst|reduce_nor~87'
        Info: 3: + IC(1.681 ns) + CELL(0.200 ns) = 4.562 ns; Loc. = LC_X3_Y3_N8; Fanout = 2; COMB Node = 'signal1:inst|reduce_nor~1'
        Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.067 ns; Loc. = LC_X3_Y3_N9; Fanout = 8; COMB Node = 'signal1:inst|tmp[2]~390'
        Info: 5: + IC(0.660 ns) + CELL(1.908 ns) = 7.635 ns; Loc. = LC_X3_Y3_N5; Fanout = 6; REG Node = 'signal1:inst|tmp[5]'
        Info: Total cell delay = 2.508 ns ( 32.85 % )
        Info: Total interconnect delay = 5.127 ns ( 67.15 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.841 ns
            Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X3_Y3_N5; Fanout = 6; REG Node = 'signal1:inst|tmp[5]'
            Info: Total cell delay = 2.574 ns ( 67.01 % )
            Info: Total interconnect delay = 1.267 ns ( 32.99 % )
        Info: - Longest clock path from clock "clk" to source register is 3.841 ns
            Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X3_Y3_N6; Fanout = 6; REG Node = 'signal1:inst|tmp[6]'
            Info: Total cell delay = 2.574 ns ( 67.01 % )
            Info: Total interconnect delay = 1.267 ns ( 32.99 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "signal1:inst|a" (data pin = "reset", clock pin = "clk") is 3.050 ns
    Info: + Longest pin to register delay is 6.558 ns
        Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_12; Fanout = 28; PIN Node = 'reset'
        Info: 2: + IC(3.659 ns) + CELL(1.243 ns) = 6.558 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst|a'
        Info: Total cell delay = 2.899 ns ( 44.21 % )
        Info: Total interconnect delay = 3.659 ns ( 55.79 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.841 ns
        Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst|a'
        Info: Total cell delay = 2.574 ns ( 67.01 % )
        Info: Total interconnect delay = 1.267 ns ( 32.99 % )
Info: tco from clock "clk" to destination pin "q[5]" through register "signal5:inst10|q[3]" is 17.165 ns
    Info: + Longest clock path from clock "clk" to source register is 3.841 ns
        Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X5_Y2_N4; Fanout = 25; REG Node = 'signal5:inst10|q[3]'
        Info: Total cell delay = 2.574 ns ( 67.01 % )
        Info: Total interconnect delay = 1.267 ns ( 32.99 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 12.948 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N4; Fanout = 25; REG Node = 'signal5:inst10|q[3]'
        Info: 2: + IC(1.012 ns) + CELL(0.914 ns) = 1.926 ns; Loc. = LC_X5_Y2_N0; Fanout = 2; COMB Node = 'signal5:inst10|display[5]~1079'
        Info: 3: + IC(1.248 ns) + CELL(0.511 ns) = 3.685 ns; Loc. = LC_X4_Y2_N4; Fanout = 1; COMB Node = 'signal5:inst10|display[5]~1082'
        Info: 4: + IC(0.757 ns) + CELL(0.511 ns) = 4.953 ns; Loc. = LC_X4_Y2_N0; Fanout = 1; COMB Node = 'signal5:inst10|display[5]~1083'
        Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.458 ns; Loc. = LC_X4_Y2_N1; Fanout = 1; COMB Node = 'selectsignal:inst7|Mux~526'
        Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 5.963 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'selectsignal:inst7|Mux~527'
        Info: 7: + IC(0.725 ns) + CELL(0.200 ns) = 6.888 ns; Loc. = LC_X4_Y2_N5; Fanout = 2; COMB Node = 'selectsignal:inst7|Mux~528'
        Info: 8: + IC(0.000 ns) + CELL(1.882 ns) = 8.770 ns; Loc. = LC_X3_Y2_N2; Fanout = 2; COMB LOOP Node = 'selectsignal:inst7|q[5]'
            Info: Loc. = LC_X3_Y2_N2; Node "selectsignal:inst7|q[5]"
        Info: 9: + IC(1.856 ns) + CELL(2.322 ns) = 12.948 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'q[5]'
        Info: Total cell delay = 6.740 ns ( 52.05 % )
        Info: Total interconnect delay = 6.208 ns ( 47.95 % )
Info: Longest tpd from source pin "sel[0]" to destination pin "q[5]" is 15.061 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_96; Fanout = 8; PIN Node = 'sel[0]'
    Info: 2: + IC(3.436 ns) + CELL(0.511 ns) = 5.079 ns; Loc. = LC_X4_Y3_N6; Fanout = 8; COMB Node = 'selectsignal:inst7|Mux~522'
    Info: 3: + IC(1.981 ns) + CELL(0.511 ns) = 7.571 ns; Loc. = LC_X4_Y2_N1; Fanout = 1; COMB Node = 'selectsignal:inst7|Mux~526'
    Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 8.076 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'selectsignal:inst7|Mux~527'
    Info: 5: + IC(0.725 ns) + CELL(0.200 ns) = 9.001 ns; Loc. = LC_X4_Y2_N5; Fanout = 2; COMB Node = 'selectsignal:inst7|Mux~528'
    Info: 6: + IC(0.000 ns) + CELL(1.882 ns) = 10.883 ns; Loc. = LC_X3_Y2_N2; Fanout = 2; COMB LOOP Node = 'selectsignal:inst7|q[5]'
        Info: Loc. = LC_X3_Y2_N2; Node "selectsignal:inst7|q[5]"
    Info: 7: + IC(1.856 ns) + CELL(2.322 ns) = 15.061 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'q[5]'
    Info: Total cell delay = 6.758 ns ( 44.87 % )
    Info: Total interconnect delay = 8.303 ns ( 55.13 % )
Info: th for register "signal1:inst|a" (data pin = "reset", clock pin = "clk") is -2.496 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.841 ns
        Info: 1: + IC(0.000 ns) + CELL(1.656 ns) = 1.656 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.841 ns; Loc. = LC_X2_Y3_N3; Fanout = 25; REG Node = 'signal1:inst|a'
        Info: Total cell delay =