signal.fit.rpt

一个简单的多种信号的发生器 包括正玄

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; Fitter Messages ;
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Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Mar 07 22:46:50 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off signal -c signal
Info: Selected device EPM240T100C5 for design "signal"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 1 pins of 13 total pins
    Info: Pin sel[2] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted signal "selectsignal:inst7|Mux~520" to use Global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock in PIN 12
    Info: Destination "signal1:inst|a" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 7 total pin(s) used --  31 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  37 pins available
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "selectsignal:5|q[0]~387" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[0]~388" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[1]~385" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[1]~386" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[2]~383" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[2]~384" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[3]~381" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[3]~382" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[4]~82" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[4]~83" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[5]~80" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[5]~81" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[6]~78" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[6]~79" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[7]~76" is assigned to location or region, but does not exist in design
    Warning: Node "selectsignal:5|q[7]~77" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|a~138" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|a~153" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|a~159" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[0]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[1]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[2]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[3]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[4]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[5]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal1:inst|tmp[6]~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|counter_cella0~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|counter_cella1~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|counter_cella2~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|counter_cella3~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|counter_cella4~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|counter_cella5~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[0]" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[1]" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[2]" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[3]" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[4]" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[5]" is assigned to location or region, but does not exist in design
    Warning: Node "signal2:inst1|lpm_counter:tmp_rtl_1|cntr_jp7:auto_generated|safe_q[6]" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella0" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella0~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella1" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella1~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella2" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella2~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella3" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella3~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella4" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella4~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella5" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella5~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella6" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella6~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal3:inst2|lpm_counter:tmp_rtl_0|cntr_rb7:auto_generated|counter_cella7" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|counter_cella0~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|counter_cella1~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|counter_cella2~COUT" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|safe_q[0]" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|safe_q[1]" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|safe_q[2]" is assigned to location or region, but does not exist in design
    Warning: Node "signal4:inst3|lpm_counter:tmp_rtl_2|cntr_p47:auto_generated|safe_q[3]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Can't open a Routing Constraints File -- routing will continue without constraints
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 13.120 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y2; Fanout = 25; REG Node = 'signal5:inst10|q[1]'
    Info: 2: + IC(1.689 ns) + CELL(0.914 ns) = 2.603 ns; Loc. = LAB_X5_Y3; Fanout = 2; COMB Node = 'signal5:inst10|display[4]~1084'
    Info: 3: + IC(1.127 ns) + CELL(0.511 ns) = 4.241 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'signal5:inst10|display[4]~1086'
    Info: 4: + IC(0.442 ns) + CELL(0.740 ns) = 5.423 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'signal5:inst10|display[4]~1088'
    Info: 5: + IC(0.268 ns) + CELL(0.914 ns) = 6.605 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'selectsignal:inst7|Mux~530'
    Info: 6: + IC(0.442 ns) + CELL(0.740 ns) = 7.787 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'selectsignal:inst7|Mux~531'
    Info: 7: + IC(0.442 ns) + CELL(0.740 ns) = 8.969 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'selectsignal:inst7|q[4]'
    Info: 8: + IC(1.829 ns) + CELL(2.322 ns) = 13.120 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'q[4]'
    Info: Total cell delay = 6.881 ns ( 52.45 % )
    Info: Total interconnect delay = 6.239 ns ( 47.55 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 62 warnings
    Info: Processing ended: Tue Mar 07 22:46:55 2006
    Info: Elapsed time: 00:00:05