fdivyear.rpt

用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能

         #  _LC1_B2 & !_LC1_B10 &  _LC3_B2;

-- Node name is ':102' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = LCELL( _EQ016);
  _EQ016 =  _LC2_B2 &  _LC6_B7 &  _LC8_B2
         #  _LC4_B7 &  _LC6_B7 &  _LC8_B2
         # !_LC2_B2 & !_LC6_B7 &  _LC8_B2
         # !_LC4_B7 & !_LC6_B7 &  _LC8_B2
         #  _LC2_B2 &  _LC4_B7 & !_LC6_B7 & !_LC8_B2;

-- Node name is ':103' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = LCELL( _EQ017);
  _EQ017 =  _LC1_B2 &  _LC2_B2 & !_LC4_B7
         # !_LC1_B2 & !_LC2_B2 & !_LC4_B7
         # !_LC1_B2 &  _LC2_B2 &  _LC4_B7
         #  _LC1_B2 & !_LC2_B2 &  _LC4_B7;

-- Node name is ':106' 
-- Equation name is '_LC7_B8', type is buried 
!_LC7_B8 = _LC7_B8~NOT;
_LC7_B8~NOT = LCELL( _EQ018);
  _EQ018 = !_LC2_B11
         # !_LC8_B12;

-- Node name is ':121' 
-- Equation name is '_LC1_B12', type is buried 
_LC1_B12 = DFFE( _EQ019, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ019 =  _LC6_B12 &  _LC8_B12;

-- Node name is ':122' 
-- Equation name is '_LC5_B12', type is buried 
_LC5_B12 = DFFE( _EQ020, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ020 =  _LC2_B11 &  _LC8_B12;

-- Node name is ':123' 
-- Equation name is '_LC7_B11', type is buried 
_LC7_B11 = DFFE( _EQ021, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ021 =  _LC4_B11 &  _LC8_B12;

-- Node name is ':124' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = DFFE( _EQ022, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ022 =  _LC4_B10 &  _LC8_B12;

-- Node name is ':125' 
-- Equation name is '_LC6_B7', type is buried 
_LC6_B7  = DFFE( _EQ023, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ023 =  _LC5_B2 &  _LC8_B12;

-- Node name is ':126' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ024, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ024 =  _LC4_B2 &  _LC8_B12;

-- Node name is ':127' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = DFFE( _EQ025, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ025 =  _LC6_B2 &  _LC8_B12;

-- Node name is ':128' 
-- Equation name is '_LC4_B7', type is buried 
_LC4_B7  = DFFE( _EQ026, GLOBAL( clki), GLOBAL(!clr),  VCC,  VCC);
  _EQ026 = !_LC4_B7 &  _LC8_B12;

-- Node name is '~367~1' 
-- Equation name is '~367~1', location is LC5_B10, type is buried.
-- synthesized logic cell 
_LC5_B10 = LCELL( _EQ027);
  _EQ027 = !_LC4_B11 & !_LC5_B2 & !_LC6_B2;

-- Node name is '~367~2' 
-- Equation name is '~367~2', location is LC3_B10, type is buried.
-- synthesized logic cell 
_LC3_B10 = LCELL( _EQ028);
  _EQ028 =  _LC4_B11 &  _LC8_B12
         #  _LC4_B2 &  _LC5_B10 &  _LC8_B12;

-- Node name is '~367~3' 
-- Equation name is '~367~3', location is LC7_B12, type is buried.
-- synthesized logic cell 
_LC7_B12 = LCELL( _EQ029);
  _EQ029 = !_LC2_B11 & !_LC6_B12;

-- Node name is '~367~4' 
-- Equation name is '~367~4', location is LC7_B10, type is buried.
-- synthesized logic cell 
_LC7_B10 = LCELL( _EQ030);
  _EQ030 = !_LC4_B10 & !_LC5_B2 & !_LC6_B2
         #  _LC4_B10 & !_LC5_B2 &  _LC6_B2;

-- Node name is '~367~5' 
-- Equation name is '~367~5', location is LC7_B2, type is buried.
-- synthesized logic cell 
_LC7_B2  = LCELL( _EQ031);
  _EQ031 =  _LC1_B10 &  _LC2_B2 &  _LC3_B2 &  _LC8_B2
         # !_LC1_B10 &  _LC2_B2 & !_LC3_B2 &  _LC8_B2;

-- Node name is '~367~6' 
-- Equation name is '~367~6', location is LC1_B8, type is buried.
-- synthesized logic cell 
_LC1_B8  = LCELL( _EQ032);
  _EQ032 = !_LC3_B11 & !_LC4_B12 &  _LC5_B2 &  _LC7_B2;

-- Node name is '~367~7' 
-- Equation name is '~367~7', location is LC3_B8, type is buried.
-- synthesized logic cell 
_LC3_B8  = LCELL( _EQ033);
  _EQ033 =  _LC3_B10 &  _LC7_B10 &  _LC7_B12
         #  _LC1_B8 &  _LC3_B10;

-- Node name is '~367~8' 
-- Equation name is '~367~8', location is LC6_B10, type is buried.
-- synthesized logic cell 
_LC6_B10 = LCELL( _EQ034);
  _EQ034 = !_LC4_B11 & !_LC5_B2 &  _LC6_B2;

-- Node name is '~367~9' 
-- Equation name is '~367~9', location is LC8_B10, type is buried.
-- synthesized logic cell 
_LC8_B10 = LCELL( _EQ035);
  _EQ035 =  _LC4_B10 &  _LC6_B10 &  _LC7_B12 &  _LC8_B12;

-- Node name is '~367~10' 
-- Equation name is '~367~10', location is LC1_B11, type is buried.
-- synthesized logic cell 
_LC1_B11 = LCELL( _EQ036);
  _EQ036 =  _LC1_B10 &  _LC3_B2 & !_LC3_B11 &  _LC7_B11
         # !_LC1_B10 & !_LC3_B11 & !_LC7_B11
         # !_LC3_B2 & !_LC3_B11 & !_LC7_B11;

-- Node name is '~367~11' 
-- Equation name is '~367~11', location is LC4_B8, type is buried.
-- synthesized logic cell 
_LC4_B8  = LCELL( _EQ037);
  _EQ037 =  _LC2_B11 &  _LC5_B2 &  _LC8_B12
         #  _LC1_B11 &  _LC5_B2 &  _LC8_B12;

-- Node name is '~367~12' 
-- Equation name is '~367~12', location is LC5_B8, type is buried.
-- synthesized logic cell 
_LC5_B8  = LCELL( _EQ038);
  _EQ038 =  _LC8_B10
         #  _LC4_B8 & !_LC4_B12 &  _LC7_B2;

-- Node name is '~367~13' 
-- Equation name is '~367~13', location is LC6_B8, type is buried.
-- synthesized logic cell 
_LC6_B8  = LCELL( _EQ039);
  _EQ039 = !_LC2_B11 & !_LC4_B11 &  _LC6_B12 &  _LC8_B12
         #  _LC2_B11 & !_LC6_B12 &  _LC8_B12;

-- Node name is '~367~14' 
-- Equation name is '~367~14', location is LC8_B8, type is buried.
-- synthesized logic cell 
_LC8_B8  = LCELL( _EQ040);
  _EQ040 =  _LC7_B10
         #  _LC5_B2 &  _LC7_B2 & !_LC7_B8;

-- Node name is '~367~15' 
-- Equation name is '~367~15', location is LC2_B8, type is buried.
-- synthesized logic cell 
_LC2_B8  = LCELL( _EQ041);
  _EQ041 =  _LC3_B8
         #  _LC5_B8
         #  _LC6_B8 &  _LC8_B8;

-- Node name is ':368' 
-- Equation name is '_LC1_B7', type is buried 
_LC1_B7  = DFFE( _EQ042, GLOBAL( clki),  VCC,  VCC, !_LC2_B7);
  _EQ042 =  _LC2_B8 &  _LC4_B7;



Project Information          e:\amj\eda\experiment\calendar_clock\fdivyear.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,031K