📄 fdivyear.rpt
字号:
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 07 SOFT s ! 1 0 0 1 clr~1
- 5 - B 11 AND2 0 3 0 1 |lpm_add_sub:370|addcore:adder|:137
- 3 - B 12 AND2 0 4 0 1 |lpm_add_sub:370|addcore:adder|:141
- 3 - B 02 AND2 0 4 0 6 |lpm_add_sub:371|addcore:adder|:129
- 8 - B 11 AND2 0 3 0 1 |lpm_add_sub:371|addcore:adder|:137
- 3 - B 11 OR2 0 4 0 3 |lpm_add_sub:371|addcore:adder|:154
- 4 - B 12 OR2 0 3 0 3 |lpm_add_sub:371|addcore:adder|:155
- 8 - B 12 OR2 0 4 0 13 :12
- 2 - B 12 OR2 0 2 0 1 :27
- 1 - B 02 OR2 0 4 0 8 :62
- 2 - B 10 OR2 ! 0 3 0 1 :64
- 5 - B 02 OR2 0 4 0 7 :93
- 6 - B 12 OR2 0 4 0 3 :97
- 2 - B 11 OR2 0 4 0 5 :98
- 4 - B 11 OR2 0 4 0 5 :99
- 4 - B 10 OR2 0 4 0 3 :100
- 4 - B 02 OR2 0 4 0 2 :102
- 6 - B 02 OR2 0 3 0 4 :103
- 7 - B 08 OR2 ! 0 2 0 1 :106
- 1 - B 12 DFFE + 0 2 1 3 :121
- 5 - B 12 DFFE + 0 2 1 5 :122
- 7 - B 11 DFFE + 0 2 1 7 :123
- 1 - B 10 DFFE + 0 2 1 9 :124
- 6 - B 07 DFFE + 0 2 1 4 :125
- 8 - B 02 DFFE + 0 2 1 6 :126
- 2 - B 02 DFFE + 0 2 1 7 :127
- 4 - B 07 DFFE + 0 1 1 7 :128
- 5 - B 10 AND2 s 0 3 0 1 ~367~1
- 3 - B 10 OR2 s 0 4 0 1 ~367~2
- 7 - B 12 AND2 s 0 2 0 2 ~367~3
- 7 - B 10 OR2 s 0 3 0 2 ~367~4
- 7 - B 02 OR2 s 0 4 0 3 ~367~5
- 1 - B 08 AND2 s 0 4 0 1 ~367~6
- 3 - B 08 OR2 s 0 4 0 1 ~367~7
- 6 - B 10 AND2 s 0 3 0 1 ~367~8
- 8 - B 10 AND2 s 0 4 0 1 ~367~9
- 1 - B 11 OR2 s 0 4 0 1 ~367~10
- 4 - B 08 OR2 s 0 4 0 1 ~367~11
- 5 - B 08 OR2 s 0 4 0 1 ~367~12
- 6 - B 08 OR2 s 0 4 0 1 ~367~13
- 8 - B 08 OR2 s 0 4 0 1 ~367~14
- 2 - B 08 OR2 s 0 4 0 1 ~367~15
- 1 - B 07 DFFE + 0 3 1 0 :368
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdivyear.rpt
fdivyear
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 28/ 48( 58%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdivyear.rpt
fdivyear
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clki
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdivyear.rpt
fdivyear
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 clr
Device-Specific Information: e:\amj\eda\experiment\calendar_clock\fdivyear.rpt
fdivyear
** EQUATIONS **
clki : INPUT;
clr : INPUT;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC2_B7, type is buried.
-- synthesized logic cell
!_LC2_B7 = _LC2_B7~NOT;
_LC2_B7~NOT = LCELL(!clr);
-- Node name is 'leapyear'
-- Equation name is 'leapyear', type is output
leapyear = _LC1_B7;
-- Node name is 'year0'
-- Equation name is 'year0', type is output
year0 = _LC4_B7;
-- Node name is 'year1'
-- Equation name is 'year1', type is output
year1 = _LC2_B2;
-- Node name is 'year2'
-- Equation name is 'year2', type is output
year2 = _LC8_B2;
-- Node name is 'year3'
-- Equation name is 'year3', type is output
year3 = _LC6_B7;
-- Node name is 'year4'
-- Equation name is 'year4', type is output
year4 = _LC1_B10;
-- Node name is 'year5'
-- Equation name is 'year5', type is output
year5 = _LC7_B11;
-- Node name is 'year6'
-- Equation name is 'year6', type is output
year6 = _LC5_B12;
-- Node name is 'year7'
-- Equation name is 'year7', type is output
year7 = _LC1_B12;
-- Node name is '|lpm_add_sub:370|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ001);
_EQ001 = !_LC1_B2 & _LC1_B10 & _LC7_B11;
-- Node name is '|lpm_add_sub:370|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B12', type is buried
_LC3_B12 = LCELL( _EQ002);
_EQ002 = !_LC1_B2 & _LC1_B10 & _LC5_B12 & _LC7_B11;
-- Node name is '|lpm_add_sub:371|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ003);
_EQ003 = _LC2_B2 & _LC4_B7 & _LC6_B7 & _LC8_B2;
-- Node name is '|lpm_add_sub:371|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ004);
_EQ004 = _LC1_B10 & _LC3_B2 & _LC7_B11;
-- Node name is '|lpm_add_sub:371|addcore:adder|:154' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ005);
_EQ005 = !_LC1_B10 & _LC5_B12
# !_LC3_B2 & _LC5_B12
# _LC5_B12 & !_LC7_B11
# _LC1_B10 & _LC3_B2 & !_LC5_B12 & _LC7_B11;
-- Node name is '|lpm_add_sub:371|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ006);
_EQ006 = _LC1_B12 & !_LC8_B11
# _LC1_B12 & !_LC5_B12
# !_LC1_B12 & _LC5_B12 & _LC8_B11;
-- Node name is ':12'
-- Equation name is '_LC8_B12', type is buried
_LC8_B12 = LCELL( _EQ007);
_EQ007 = !_LC1_B12
# _LC2_B12 & !_LC5_B12 & !_LC7_B11;
-- Node name is ':27'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ008);
_EQ008 = !_LC1_B10
# _LC1_B2;
-- Node name is ':62'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ009);
_EQ009 = !_LC6_B7
# !_LC2_B2 & !_LC4_B7 & !_LC8_B2;
-- Node name is ':64'
-- Equation name is '_LC2_B10', type is buried
!_LC2_B10 = _LC2_B10~NOT;
_LC2_B10~NOT = LCELL( _EQ010);
_EQ010 = _LC2_B2
# _LC4_B7
# _LC8_B2;
-- Node name is ':93'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ011);
_EQ011 = _LC2_B2 & _LC4_B7 & !_LC6_B7 & _LC8_B2
# !_LC2_B2 & !_LC4_B7 & _LC6_B7 & !_LC8_B2;
-- Node name is ':97'
-- Equation name is '_LC6_B12', type is buried
_LC6_B12 = LCELL( _EQ012);
_EQ012 = !_LC1_B2 & _LC1_B12 & !_LC3_B12
# !_LC1_B2 & !_LC1_B12 & _LC3_B12
# _LC1_B2 & _LC4_B12;
-- Node name is ':98'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ013);
_EQ013 = !_LC1_B2 & !_LC5_B11 & _LC5_B12
# !_LC1_B2 & _LC5_B11 & !_LC5_B12
# _LC1_B2 & _LC3_B11;
-- Node name is ':99'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ014);
_EQ014 = !_LC1_B2 & _LC1_B10 & !_LC7_B11
# !_LC1_B10 & _LC7_B11
# _LC1_B2 & !_LC3_B2 & _LC7_B11
# _LC1_B10 & _LC3_B2 & !_LC7_B11;
-- Node name is ':100'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ015);
_EQ015 = !_LC1_B2 & _LC1_B10 & _LC2_B10
# !_LC1_B2 & !_LC1_B10 & !_LC2_B10
# _LC1_B2 & _LC1_B10 & !_LC3_B2
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