📄 fdiv_cnt_new.rpt
字号:
- 4 - C 14 DFFE ! 0 2 1 8 |fdiv12:70|:107
- 4 - C 15 AND2 s 0 4 0 2 |fdiv12:70|~108~1
- 8 - C 19 DFFE 0 3 1 1 |fdiv12:70|:118
- 2 - B 06 AND2 s 0 3 0 1 |fdiv24:55|lpm_add_sub:96|addcore:adder|~137~1
- 3 - B 06 OR2 0 4 0 2 |fdiv24:55|lpm_add_sub:96|addcore:adder|:137
- 6 - B 06 OR2 0 3 0 1 |fdiv24:55|lpm_add_sub:96|addcore:adder|:155
- 8 - B 05 OR2 ! 0 2 0 6 |fdiv24:55|lpm_add_sub:97|addcore:adder|:121
- 5 - B 03 AND2 0 2 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:125
- 6 - B 03 AND2 0 3 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:129
- 1 - B 03 AND2 0 4 0 3 |fdiv24:55|lpm_add_sub:97|addcore:adder|:133
- 4 - B 06 AND2 0 2 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:137
- 7 - B 06 OR2 0 4 0 1 |fdiv24:55|lpm_add_sub:97|addcore:adder|:155
- 1 - B 05 OR2 s 0 4 0 2 |fdiv24:55|~12~1
- 4 - B 05 OR2 ! 0 4 0 7 |fdiv24:55|:12
- 2 - B 05 OR2 ! 0 4 0 7 |fdiv24:55|:30
- 5 - B 06 OR2 0 4 0 1 |fdiv24:55|:54
- 8 - B 03 OR2 0 4 0 1 |fdiv24:55|:55
- 8 - B 06 DFFE 0 5 1 3 |fdiv24:55|:77
- 1 - B 06 DFFE 0 3 1 5 |fdiv24:55|:78
- 4 - B 03 DFFE 0 3 1 5 |fdiv24:55|:79
- 7 - B 03 DFFE 0 4 1 5 |fdiv24:55|:80
- 2 - B 03 DFFE 0 4 1 5 |fdiv24:55|:81
- 3 - B 03 DFFE 0 4 1 6 |fdiv24:55|:82
- 6 - B 05 DFFE 0 4 1 3 |fdiv24:55|:83
- 5 - B 05 DFFE 0 1 1 4 |fdiv24:55|:84
- 3 - B 05 DFFE 0 5 1 2 |fdiv24:55|:95
- 3 - B 22 OR2 ! 0 4 0 3 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:129
- 2 - B 15 OR2 0 2 0 1 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:149
- 7 - B 15 OR2 0 3 0 1 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:150
- 8 - B 15 OR2 0 4 0 1 |fdiv28_31:57|lpm_add_sub:555|addcore:adder|:151
- 7 - C 15 OR2 ! 0 2 0 7 |fdiv28_31:57|:21
- 3 - B 16 OR2 ! 0 4 0 2 |fdiv28_31:57|:43
- 1 - B 15 OR2 ! 0 3 0 1 |fdiv28_31:57|:55
- 1 - B 14 OR2 ! 0 2 0 4 |fdiv28_31:57|:74
- 4 - B 14 OR2 0 4 0 1 |fdiv28_31:57|:99
- 5 - B 16 OR2 ! 0 4 0 2 |fdiv28_31:57|:132
- 2 - B 16 OR2 s 0 4 0 3 |fdiv28_31:57|~232~1
- 8 - B 14 AND2 s 0 2 0 3 |fdiv28_31:57|~232~2
- 6 - C 15 OR2 s 0 2 0 1 |fdiv28_31:57|~281~1
- 1 - C 15 OR2 ! 0 4 0 3 |fdiv28_31:57|:281
- 4 - B 16 AND2 ! 0 2 0 3 |fdiv28_31:57|:292
- 1 - B 22 OR2 ! 0 4 0 2 |fdiv28_31:57|:396
- 8 - B 16 OR2 s 0 4 0 3 |fdiv28_31:57|~481~1
- 4 - B 15 AND2 s 0 2 0 3 |fdiv28_31:57|~481~2
- 6 - B 14 OR2 s 0 4 0 1 |fdiv28_31:57|~492~1
- 3 - B 14 OR2 s 0 3 0 2 |fdiv28_31:57|~494~1
- 1 - B 16 OR2 s 0 4 0 1 |fdiv28_31:57|~498~1
- 7 - B 16 OR2 s 0 4 0 1 |fdiv28_31:57|~498~2
- 2 - B 14 DFFE 0 4 1 7 |fdiv28_31:57|:500
- 7 - B 14 DFFE 0 5 1 6 |fdiv28_31:57|:501
- 5 - B 14 DFFE 0 4 1 6 |fdiv28_31:57|:502
- 5 - B 15 DFFE 0 5 1 7 |fdiv28_31:57|:503
- 6 - B 15 DFFE 0 5 1 7 |fdiv28_31:57|:504
- 3 - B 15 DFFE 0 5 1 8 |fdiv28_31:57|:505
- 6 - B 16 DFFE 0 4 1 10 |fdiv28_31:57|:506
- 2 - B 22 AND2 s 0 3 0 1 |fdiv28_31:57|~527~1
- 8 - B 22 AND2 s 0 3 0 3 |fdiv28_31:57|~527~2
- 5 - B 22 OR2 0 4 0 1 |fdiv28_31:57|:527
- 6 - B 22 AND2 s 0 4 0 1 |fdiv28_31:57|~549~1
- 7 - B 22 OR2 0 4 0 1 |fdiv28_31:57|:549
- 4 - B 22 DFFE 0 5 1 1 |fdiv28_31:57|:552
- 2 - B 12 AND2 s 0 3 0 1 |fdiv60:53|lpm_add_sub:96|addcore:adder|~137~1
- 1 - B 23 OR2 0 4 0 2 |fdiv60:53|lpm_add_sub:96|addcore:adder|:137
- 6 - B 23 AND2 0 3 0 3 |fdiv60:53|lpm_add_sub:97|addcore:adder|:125
- 6 - B 12 AND2 0 2 0 2 |fdiv60:53|lpm_add_sub:97|addcore:adder|:129
- 3 - B 12 AND2 0 4 0 2 |fdiv60:53|lpm_add_sub:97|addcore:adder|:137
- 3 - B 11 AND2 s ! 0 4 0 5 |fdiv60:53|~12~1
- 3 - B 23 AND2 0 4 0 9 |fdiv60:53|:30
- 4 - B 11 OR2 0 4 0 1 |fdiv60:53|:36
- 5 - B 11 OR2 0 4 0 1 |fdiv60:53|:45
- 2 - B 11 OR2 0 4 0 1 |fdiv60:53|:54
- 8 - B 12 OR2 0 4 0 1 |fdiv60:53|:55
- 8 - B 11 DFFE 0 5 1 3 |fdiv60:53|:77
- 1 - B 11 DFFE 0 4 1 4 |fdiv60:53|:78
- 1 - B 12 DFFE 0 4 1 4 |fdiv60:53|:79
- 7 - B 12 DFFE 0 4 1 7 |fdiv60:53|:80
- 4 - B 12 DFFE 0 3 1 4 |fdiv60:53|:81
- 4 - B 23 DFFE 0 4 1 3 |fdiv60:53|:82
- 2 - B 23 DFFE 0 3 1 4 |fdiv60:53|:83
- 8 - B 23 DFFE 0 1 1 5 |fdiv60:53|:84
- 5 - B 12 DFFE 0 3 1 1 |fdiv60:53|:95
- 2 - A 06 AND2 s 0 3 0 1 |fdiv60:54|lpm_add_sub:96|addcore:adder|~137~1
- 1 - A 05 OR2 0 4 0 2 |fdiv60:54|lpm_add_sub:96|addcore:adder|:137
- 8 - A 05 AND2 0 3 0 3 |fdiv60:54|lpm_add_sub:97|addcore:adder|:125
- 5 - A 06 AND2 0 2 0 2 |fdiv60:54|lpm_add_sub:97|addcore:adder|:129
- 3 - A 06 AND2 0 4 0 2 |fdiv60:54|lpm_add_sub:97|addcore:adder|:137
- 1 - A 03 AND2 s ! 0 4 0 5 |fdiv60:54|~12~1
- 5 - A 05 AND2 0 4 0 9 |fdiv60:54|:30
- 7 - A 03 OR2 0 4 0 1 |fdiv60:54|:36
- 8 - A 03 OR2 0 4 0 1 |fdiv60:54|:45
- 4 - A 03 OR2 0 4 0 1 |fdiv60:54|:54
- 6 - A 06 OR2 0 4 0 1 |fdiv60:54|:55
- 6 - A 03 DFFE 0 5 1 3 |fdiv60:54|:77
- 3 - A 03 DFFE 0 4 1 4 |fdiv60:54|:78
- 1 - A 06 DFFE 0 4 1 4 |fdiv60:54|:79
- 4 - A 06 DFFE 0 4 1 7 |fdiv60:54|:80
- 7 - A 06 DFFE 0 3 1 4 |fdiv60:54|:81
- 6 - A 05 DFFE 0 4 1 3 |fdiv60:54|:82
- 4 - A 05 DFFE 0 3 1 4 |fdiv60:54|:83
- 7 - A 05 DFFE 0 1 1 5 |fdiv60:54|:84
- 5 - A 03 DFFE 0 3 1 1 |fdiv60:54|:95
- 5 - C 01 AND2 0 2 0 4 |fdiv100:52|lpm_add_sub:51|addcore:adder|:121
- 1 - C 01 AND2 0 2 0 3 |fdiv100:52|lpm_add_sub:51|addcore:adder|:125
- 4 - C 02 AND2 0 3 0 3 |fdiv100:52|lpm_add_sub:51|addcore:adder|:133
- 7 - C 02 AND2 0 2 0 1 |fdiv100:52|lpm_add_sub:51|addcore:adder|:137
- 1 - C 02 OR2 s 0 4 0 2 |fdiv100:52|~4~1
- 3 - C 01 OR2 ! 0 4 0 7 |fdiv100:52|:4
- 8 - C 02 DFFE + 0 3 0 1 |fdiv100:52|cnt7 (|fdiv100:52|:32)
- 6 - C 02 DFFE + 0 3 0 2 |fdiv100:52|cnt6 (|fdiv100:52|:33)
- 5 - C 02 DFFE + 0 2 0 3 |fdiv100:52|cnt5 (|fdiv100:52|:34)
- 3 - C 02 DFFE + 0 3 0 2 |fdiv100:52|cnt4 (|fdiv100:52|:35)
- 2 - C 02 DFFE + 0 2 0 4 |fdiv100:52|cnt3 (|fdiv100:52|:36)
- 8 - C 01 DFFE + 0 2 0 3 |fdiv100:52|cnt2 (|fdiv100:52|:37)
- 6 - C 01 DFFE + 0 2 0 1 |fdiv100:52|cnt1 (|fdiv100:52|:38)
- 7 - C 01 DFFE + 0 0 0 2 |fdiv100:52|cnt0 (|fdiv100:52|:39)
- 2 - C 01 DFFE + 0 4 1 1 |fdiv100:52|:50
- 4 - C 01 OR2 1 1 0 9 :63
- 3 - A 05 OR2 1 1 0 9 :64
- 2 - A 03 OR2 1 1 0 9 :65
- 2 - A 20 OR2 1 1 0 4 :66
- 1 - B 24 OR2 1 1 0 8 :67
- 1 - C 22 OR2 1 1 0 6 :68
- 3 - C 19 OR2 1 1 0 9 :69
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 16/ 48( 33%) 3/ 48( 6%) 1/16( 6%) 14/16( 87%) 0/16( 0%)
B: 11/ 96( 11%) 15/ 48( 31%) 22/ 48( 45%) 0/16( 0%) 14/16( 87%) 0/16( 0%)
C: 13/ 96( 13%) 5/ 48( 10%) 32/ 48( 66%) 1/16( 6%) 13/16( 81%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
LCELL 9 :63
LCELL 9 :64
LCELL 9 :65
LCELL 9 :69
LCELL 8 :67
LCELL 6 :68
LCELL 4 :66
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 32 clr_time
INPUT 25 clr_date
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** EQUATIONS **
clk : INPUT;
clr_date : INPUT;
clr_time : INPUT;
set_day : INPUT;
set_hr : INPUT;
set_min : INPUT;
set_mon : INPUT;
set_sec : INPUT;
set_week : INPUT;
set_year : INPUT;
-- Node name is 'clr_date~1'
-- Equation name is 'clr_date~1', location is LC1_A17, type is buried.
-- synthesized logic cell
!_LC1_A17 = _LC1_A17~NOT;
_LC1_A17~NOT = LCELL(!clr_date);
-- Node name is 'day_clk'
-- Equation name is 'day_clk', type is output
day_clk = _LC3_B5;
-- Node name is 'day0'
-- Equation name is 'day0', type is output
day0 = _LC6_B16;
-- Node name is 'day1'
-- Equation name is 'day1', type is output
day1 = _LC3_B15;
-- Node name is 'day2'
-- Equation name is 'day2', type is output
day2 = _LC6_B15;
-- Node name is 'day3'
-- Equation name is 'day3', type is output
day3 = _LC5_B15;
-- Node name is 'day4'
-- Equation name is 'day4', type is output
day4 = _LC5_B14;
-- Node name is 'day5'
-- Equation name is 'day5', type is output
day5 = _LC7_B14;
-- Node name is 'day6'
-- Equation name is 'day6', type is output
day6 = _LC2_B14;
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