📄 fdiv_cnt_new.rpt
字号:
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A3 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
A5 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 4/22( 18%)
A6 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
A17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
A20 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 2/22( 9%)
B3 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
B5 7/ 8( 87%) 1/ 8( 12%) 6/ 8( 75%) 1/2 1/2 7/22( 31%)
B6 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 10/22( 45%)
B11 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
B12 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
B14 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 7/22( 31%)
B15 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
B16 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
B22 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
B23 6/ 8( 75%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
B24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 3/22( 13%)
C2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 2/22( 9%)
C14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
C15 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
C16 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 3/22( 13%)
C18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 6/22( 27%)
C19 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 12/22( 54%)
C20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
C22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C23 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 13/22( 59%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 62/96 ( 64%)
Total logic cells used: 176/576 ( 30%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.27/4 ( 81%)
Total fan-in: 576/2304 ( 25%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 58
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 176
Total flipflops required: 63
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 32/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 8 0 7 7 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 28/0
B: 0 0 8 0 7 8 0 0 0 0 6 8 0 0 8 8 8 0 0 0 0 0 8 6 1 76/0
C: 8 8 0 0 0 0 0 0 0 0 0 0 0 0 8 7 8 0 8 8 8 0 1 8 0 72/0
Total: 8 8 16 0 14 15 0 0 0 0 6 8 0 0 16 15 16 1 8 8 13 0 9 14 1 176/0
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
56 - - - -- INPUT G 0 0 0 1 clr_date
54 - - - -- INPUT G 0 0 0 0 clr_time
42 - - - 19 INPUT 0 0 0 1 set_day
124 - - - -- INPUT 0 0 0 1 set_hr
126 - - - -- INPUT 0 0 0 1 set_min
46 - - - 17 INPUT 0 0 0 1 set_mon
125 - - - -- INPUT 0 0 0 1 set_sec
9 - - A -- INPUT 0 0 0 1 set_week
79 - - C -- INPUT 0 0 0 1 set_year
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - - 06 OUTPUT 0 1 0 0 day_clk
48 - - - 15 OUTPUT 0 1 0 0 day0
19 - - B -- OUTPUT 0 1 0 0 day1
47 - - - 16 OUTPUT 0 1 0 0 day2
132 - - - 16 OUTPUT 0 1 0 0 day3
22 - - B -- OUTPUT 0 1 0 0 day4
23 - - B -- OUTPUT 0 1 0 0 day5
51 - - - 13 OUTPUT 0 1 0 0 day6
142 - - - 23 OUTPUT 0 0 0 0 day7
98 - - A -- OUTPUT 0 1 0 0 h_clk
21 - - B -- OUTPUT 0 1 0 0 hr0
88 - - B -- OUTPUT 0 1 0 0 hr1
113 - - - 03 OUTPUT 0 1 0 0 hr2
112 - - - 03 OUTPUT 0 1 0 0 hr3
87 - - B -- OUTPUT 0 1 0 0 hr4
90 - - B -- OUTPUT 0 1 0 0 hr5
17 - - B -- OUTPUT 0 1 0 0 hr6
89 - - B -- OUTPUT 0 1 0 0 hr7
62 - - - 11 OUTPUT 0 1 0 0 min_clk
96 - - A -- OUTPUT 0 1 0 0 min0
99 - - A -- OUTPUT 0 1 0 0 min1
12 - - A -- OUTPUT 0 1 0 0 min2
95 - - A -- OUTPUT 0 1 0 0 min3
102 - - A -- OUTPUT 0 1 0 0 min4
101 - - A -- OUTPUT 0 1 0 0 min5
100 - - A -- OUTPUT 0 1 0 0 min6
97 - - A -- OUTPUT 0 1 0 0 min7
140 - - - 21 OUTPUT 0 1 0 0 mon_clk
83 - - C -- OUTPUT 0 1 0 0 mon0
33 - - C -- OUTPUT 0 1 0 0 mon1
81 - - C -- OUTPUT 0 1 0 0 mon2
27 - - C -- OUTPUT 0 1 0 0 mon3
32 - - C -- OUTPUT 0 1 0 0 mon4
141 - - - 22 OUTPUT 0 0 0 0 mon5
59 - - - 12 OUTPUT 0 0 0 0 mon6
7 - - A -- OUTPUT 0 0 0 0 mon7
82 - - C -- OUTPUT 0 1 0 0 s_clk
36 - - - 24 OUTPUT 0 1 0 0 sec0
18 - - B -- OUTPUT 0 1 0 0 sec1
143 - - - 24 OUTPUT 0 1 0 0 sec2
20 - - B -- OUTPUT 0 1 0 0 sec3
86 - - B -- OUTPUT 0 1 0 0 sec4
91 - - B -- OUTPUT 0 1 0 0 sec5
92 - - B -- OUTPUT 0 1 0 0 sec6
60 - - - 12 OUTPUT 0 1 0 0 sec7
14 - - A -- OUTPUT 0 1 0 0 week0
13 - - A -- OUTPUT 0 1 0 0 week1
11 - - A -- OUTPUT 0 1 0 0 week2
8 - - A -- OUTPUT 0 1 0 0 week3
136 - - - 19 OUTPUT 0 1 0 0 year_clk
31 - - C -- OUTPUT 0 1 0 0 year0
29 - - C -- OUTPUT 0 1 0 0 year1
30 - - C -- OUTPUT 0 1 0 0 year2
28 - - C -- OUTPUT 0 1 0 0 year3
78 - - C -- OUTPUT 0 1 0 0 year4
80 - - C -- OUTPUT 0 1 0 0 year5
26 - - C -- OUTPUT 0 1 0 0 year6
137 - - - 19 OUTPUT 0 1 0 0 year7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\c&c\scheme2\fdiv_cnt_new.rpt
fdiv_cnt_new
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 17 SOFT s ! 1 0 0 2 clr_date~1
- 3 - C 18 OR2 ! 0 2 0 1 |fdivyear:59|lpm_add_sub:370|addcore:adder|:133
- 5 - C 18 AND2 0 4 0 1 |fdivyear:59|lpm_add_sub:370|addcore:adder|:141
- 6 - C 18 OR2 0 4 0 2 |fdivyear:59|lpm_add_sub:370|addcore:adder|:154
- 6 - C 16 AND2 0 3 0 3 |fdivyear:59|lpm_add_sub:371|addcore:adder|:125
- 2 - C 16 AND2 0 2 0 6 |fdivyear:59|lpm_add_sub:371|addcore:adder|:129
- 4 - C 18 AND2 0 4 0 2 |fdivyear:59|lpm_add_sub:371|addcore:adder|:141
- 6 - C 19 OR2 0 3 0 1 |fdivyear:59|lpm_add_sub:371|addcore:adder|:153
- 2 - C 18 OR2 0 4 0 3 |fdivyear:59|lpm_add_sub:371|addcore:adder|:154
- 7 - C 18 OR2 0 4 0 14 |fdivyear:59|:12
- 7 - C 16 OR2 0 4 0 12 |fdivyear:59|:62
- 2 - C 19 OR2 ! 0 3 0 1 |fdivyear:59|:64
- 8 - C 16 OR2 ! 0 3 0 2 |fdivyear:59|:93
- 3 - C 20 OR2 ! 0 4 0 3 |fdivyear:59|:97
- 8 - C 18 OR2 ! 0 3 0 2 |fdivyear:59|:98
- 7 - C 23 OR2 ! 0 4 0 3 |fdivyear:59|:99
- 4 - C 19 OR2 0 4 0 2 |fdivyear:59|:100
- 1 - C 16 OR2 0 4 0 2 |fdivyear:59|:102
- 1 - C 19 OR2 0 3 0 2 |fdivyear:59|:103
- 1 - C 20 AND2 0 2 0 3 |fdivyear:59|:106
- 3 - C 23 AND2 0 2 0 3 |fdivyear:59|:107
- 4 - C 20 DFFE 0 3 1 3 |fdivyear:59|:121
- 1 - C 18 DFFE 0 5 1 5 |fdivyear:59|:122
- 4 - C 23 DFFE 0 3 1 7 |fdivyear:59|:123
- 7 - C 19 DFFE 0 3 1 9 |fdivyear:59|:124
- 3 - C 16 DFFE 0 4 1 4 |fdivyear:59|:125
- 5 - C 23 DFFE 0 3 1 5 |fdivyear:59|:126
- 4 - C 16 DFFE 0 4 1 6 |fdivyear:59|:127
- 5 - C 16 DFFE 0 2 1 7 |fdivyear:59|:128
- 2 - C 23 AND2 s 0 4 0 1 |fdivyear:59|~367~1
- 2 - C 20 OR2 s 0 4 0 1 |fdivyear:59|~367~2
- 5 - C 20 AND2 s 0 4 0 2 |fdivyear:59|~367~3
- 7 - C 20 OR2 s 0 4 0 1 |fdivyear:59|~367~4
- 8 - C 23 OR2 s 0 4 0 1 |fdivyear:59|~367~5
- 5 - C 19 OR2 s 0 4 0 1 |fdivyear:59|~367~6
- 6 - C 23 OR2 s 0 4 0 1 |fdivyear:59|~367~7
- 8 - C 20 OR2 s 0 4 0 1 |fdivyear:59|~367~8
- 6 - C 20 OR2 s 0 4 0 1 |fdivyear:59|~367~9
- 1 - C 23 DFFE 0 5 0 3 |fdivyear:59|:368
- 1 - A 20 DFFE 0 4 1 1 |fdiv7:58|:24
- 8 - A 20 DFFE 0 3 1 2 |fdiv7:58|:25
- 6 - A 20 DFFE 0 2 1 3 |fdiv7:58|:26
- 7 - A 20 DFFE ! 0 4 1 3 |fdiv7:58|:27
- 5 - C 15 AND2 0 3 0 1 |fdiv12:70|lpm_add_sub:119|addcore:adder|:125
- 2 - C 15 AND2 0 4 0 1 |fdiv12:70|lpm_add_sub:119|addcore:adder|:129
- 3 - C 14 OR2 0 4 0 5 |fdiv12:70|:27
- 3 - C 15 OR2 s ! 0 3 0 1 |fdiv12:70|~53~1
- 5 - C 14 OR2 ! 0 4 0 4 |fdiv12:70|:53
- 8 - C 14 AND2 s 0 2 0 1 |fdiv12:70|~88~1
- 6 - C 14 DFFE 0 4 1 4 |fdiv12:70|:103
- 1 - C 14 DFFE 0 4 1 5 |fdiv12:70|:104
- 2 - C 14 DFFE 0 4 1 7 |fdiv12:70|:105
- 7 - C 14 DFFE 0 4 1 7 |fdiv12:70|:106
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