scan_disp.rpt

用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能

-- Node name is '~733~1' 
-- Equation name is '~733~1', location is LC4_A11, type is buried.
-- synthesized logic cell 
_LC4_A11 = LCELL( _EQ065);
  _EQ065 =  _LC7_A1 &  sec6
         #  _LC3_A1 &  min2;

-- Node name is '~733~2' 
-- Equation name is '~733~2', location is LC2_A11, type is buried.
-- synthesized logic cell 
_LC2_A11 = LCELL( _EQ066);
  _EQ066 =  _LC2_A1 &  sec2
         #  _LC4_A11;

-- Node name is '~733~3' 
-- Equation name is '~733~3', location is LC1_A22, type is buried.
-- synthesized logic cell 
_LC1_A22 = LCELL( _EQ067);
  _EQ067 =  hour6 &  _LC6_A12
         #  _LC2_A11;

-- Node name is '~733~4' 
-- Equation name is '~733~4', location is LC7_A21, type is buried.
-- synthesized logic cell 
_LC7_A21 = LCELL( _EQ068);
  _EQ068 =  _LC7_A12 &  min6
         #  hour2 &  _LC1_A1;

-- Node name is '~734~1' 
-- Equation name is '~734~1', location is LC5_A19, type is buried.
-- synthesized logic cell 
_LC5_A19 = LCELL( _EQ069);
  _EQ069 =  _LC7_A1 &  sec5
         #  _LC3_A1 &  min1;

-- Node name is '~734~2' 
-- Equation name is '~734~2', location is LC4_A19, type is buried.
-- synthesized logic cell 
_LC4_A19 = LCELL( _EQ070);
  _EQ070 =  _LC2_A1 &  sec1
         #  _LC5_A19;

-- Node name is '~734~3' 
-- Equation name is '~734~3', location is LC1_A17, type is buried.
-- synthesized logic cell 
_LC1_A17 = LCELL( _EQ071);
  _EQ071 =  hour5 &  _LC6_A12
         #  _LC4_A19;

-- Node name is '~734~4' 
-- Equation name is '~734~4', location is LC2_A17, type is buried.
-- synthesized logic cell 
_LC2_A17 = LCELL( _EQ072);
  _EQ072 =  _LC7_A12 &  min5
         #  hour1 &  _LC1_A1;

-- Node name is '~735~1' 
-- Equation name is '~735~1', location is LC2_A19, type is buried.
-- synthesized logic cell 
_LC2_A19 = LCELL( _EQ073);
  _EQ073 =  _LC7_A1 &  sec4
         #  _LC3_A1 &  min0;

-- Node name is '~735~2' 
-- Equation name is '~735~2', location is LC6_A19, type is buried.
-- synthesized logic cell 
_LC6_A19 = LCELL( _EQ074);
  _EQ074 =  _LC2_A1 &  sec0
         #  _LC2_A19;

-- Node name is '~735~3' 
-- Equation name is '~735~3', location is LC1_A23, type is buried.
-- synthesized logic cell 
_LC1_A23 = LCELL( _EQ075);
  _EQ075 =  hour4 &  _LC6_A12
         #  _LC6_A19;

-- Node name is '~735~4' 
-- Equation name is '~735~4', location is LC2_A23, type is buried.
-- synthesized logic cell 
_LC2_A23 = LCELL( _EQ076);
  _EQ076 =  _LC7_A12 &  min4
         #  hour0 &  _LC1_A1;

-- Node name is ':736' 
-- Equation name is '_LC3_A8', type is buried 
_LC3_A8  = LCELL( _EQ077);
  _EQ077 =  _LC1_A8 & !_LC1_A18
         # !_LC1_A18 &  _LC2_A8
         # !_LC1_A18 &  _LC6_A3;

-- Node name is ':737' 
-- Equation name is '_LC3_A22', type is buried 
_LC3_A22 = LCELL( _EQ078);
  _EQ078 = !_LC1_A18 &  _LC1_A22
         # !_LC1_A18 &  _LC7_A21
         # !_LC1_A18 &  _LC2_A22;

-- Node name is ':738' 
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = LCELL( _EQ079);
  _EQ079 =  _LC1_A17 & !_LC1_A18
         # !_LC1_A18 &  _LC2_A17
         # !_LC1_A18 &  _LC5_A18;

-- Node name is ':739' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ080);
  _EQ080 = !_LC1_A18 &  _LC1_A23
         # !_LC1_A18 &  _LC2_A23
         # !_LC1_A18 &  _LC7_A13;

-- Node name is '~740~1' 
-- Equation name is '~740~1', location is LC8_A8, type is buried.
-- synthesized logic cell 
_LC8_A8  = LCELL( _EQ081);
  _EQ081 =  disp_mode0 & !disp_mode1 &  _LC3_A3
         #  disp_mode0 &  disp_mode1 &  _LC7_A8;

-- Node name is '~741~1' 
-- Equation name is '~741~1', location is LC8_A22, type is buried.
-- synthesized logic cell 
_LC8_A22 = LCELL( _EQ082);
  _EQ082 =  disp_mode0 & !disp_mode1 &  _LC6_A22
         #  disp_mode0 &  disp_mode1 &  _LC7_A22;

-- Node name is '~742~1' 
-- Equation name is '~742~1', location is LC8_A17, type is buried.
-- synthesized logic cell 
_LC8_A17 = LCELL( _EQ083);
  _EQ083 =  disp_mode0 & !disp_mode1 &  _LC6_A18
         #  disp_mode0 &  disp_mode1 &  _LC7_A17;

-- Node name is '~743~1' 
-- Equation name is '~743~1', location is LC8_A23, type is buried.
-- synthesized logic cell 
_LC8_A23 = LCELL( _EQ084);
  _EQ084 =  disp_mode0 & !disp_mode1 &  _LC4_A23
         #  disp_mode0 &  disp_mode1 &  _LC6_A23;

-- Node name is ':744' 
-- Equation name is '_LC5_A8', type is buried 
_LC5_A8  = DFFE( _EQ085, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ085 =  _LC3_A8
         #  _LC4_A17 &  week3
         #  _LC8_A8;

-- Node name is ':745' 
-- Equation name is '_LC4_A22', type is buried 
_LC4_A22 = DFFE( _EQ086, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ086 =  _LC3_A22
         #  _LC4_A17 &  week2
         #  _LC8_A22;

-- Node name is ':746' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = DFFE( _EQ087, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ087 =  _LC3_A17
         #  _LC4_A17 &  week1
         #  _LC8_A17;

-- Node name is ':747' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = DFFE( _EQ088, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ088 =  _LC3_A23
         #  _LC4_A17 &  week0
         #  _LC8_A23;

-- Node name is ':784' 
-- Equation name is '_LC2_A4', type is buried 
!_LC2_A4 = _LC2_A4~NOT;
_LC2_A4~NOT = LCELL( _EQ089);
  _EQ089 =  sel1
         # !sel0
         #  clk_4Hz;

-- Node name is ':798' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = LCELL( _EQ090);
  _EQ090 =  _LC1_A1 & !sel0
         #  clk_4Hz &  _LC1_A1
         #  _LC1_A1 &  sel1;

-- Node name is ':825' 
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ091);
  _EQ091 =  _LC7_A12 &  sel0
         #  clk_4Hz &  _LC7_A12
         #  _LC7_A12 & !sel1;

-- Node name is ':854' 
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = LCELL( _EQ092);
  _EQ092 =  _LC3_A1 &  sel0
         #  clk_4Hz &  _LC3_A1
         #  _LC3_A1 & !sel1;

-- Node name is ':879' 
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = LCELL( _EQ093);
  _EQ093 = !_LC2_A4 &  _LC6_A12
         # !_LC2_A13 &  _LC4_A12;

-- Node name is ':1021' 
-- Equation name is '_LC4_A18', type is buried 
_LC4_A18 = LCELL( _EQ094);
  _EQ094 =  _LC7_A1 & !sel0
         #  clk_4Hz &  _LC7_A1
         #  _LC7_A1 & !sel1;

-- Node name is ':1052' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = LCELL( _EQ095);
  _EQ095 =  _LC2_A1 & !sel0
         #  clk_4Hz &  _LC2_A1
         #  _LC2_A1 & !sel1;

-- Node name is ':1064' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ096);
  _EQ096 =  _LC1_A3 & !_LC6_A12 &  _LC6_A13 & !_LC8_A13;

-- Node name is ':1065' 
-- Equation name is '_LC3_A18', type is buried 
_LC3_A18 = LCELL( _EQ097);
  _EQ097 =  _LC1_A3 &  _LC2_A18 & !_LC6_A12 & !_LC8_A13;

-- Node name is ':1285' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = DFFE( _EQ098, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ098 =  disp_mode0 &  _LC1_A13
         # !disp_mode1 &  _LC1_A13
         # !disp_mode1 &  _LC3_A13;

-- Node name is ':1286' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = DFFE( _EQ099, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ099 =  disp_mode0 &  _LC3_A18
         # !disp_mode1 &  _LC3_A18
         # !disp_mode1 &  _LC4_A18;

-- Node name is ':1287' 
-- Equation name is '_LC6_A4', type is buried 
_LC6_A4  = DFFE( _EQ100, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ100 =  _LC5_A4 &  _LC8_A12
         # !_LC2_A13 &  _LC6_A4 &  _LC8_A12;

-- Node name is ':1288' 
-- Equation name is '_LC8_A4', type is buried 
_LC8_A4  = DFFE( _EQ101, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ101 =  _LC4_A4 &  _LC8_A12
         # !_LC2_A13 &  _LC8_A4 &  _LC8_A12;

-- Node name is ':1289' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = DFFE( _EQ102, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ102 =  _LC3_A4 &  _LC8_A12
         #  _LC1_A4 & !_LC2_A13 &  _LC8_A12;

-- Node name is ':1290' 
-- Equation name is '_LC4_A12', type is buried 
_LC4_A12 = DFFE( _EQ103, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ103 =  _LC7_A4 &  _LC8_A12
         #  _LC4_A17;



Project Information         e:\amj\eda\experiment\calendar_clock\scan_disp.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 28,192K