📄 scan_disp.rpt
字号:
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 12 OR2 0 3 0 22 :89
- 1 - A 01 AND2 0 3 0 15 :119
- 7 - A 12 AND2 0 3 0 16 :144
- 3 - A 01 AND2 0 3 0 15 :169
- 7 - A 01 AND2 0 3 0 10 :194
- 2 - A 01 AND2 0 3 0 11 :219
- 8 - A 13 OR2 0 3 0 8 :245
- 2 - A 12 OR2 0 4 0 1 :246
- 4 - A 17 AND2 2 0 0 9 :250
- 5 - A 01 OR2 0 4 0 1 :263
- 4 - A 01 OR2 0 4 0 1 :264
- 1 - A 18 AND2 ! 2 0 0 4 :435
- 8 - A 12 OR2 s 1 1 0 7 ~602~1
- 8 - A 01 DFFE + 0 4 0 9 state2 (:605)
- 6 - A 01 DFFE + 0 3 0 9 state1 (:606)
- 3 - A 12 DFFE + 0 3 0 9 state0 (:607)
- 1 - A 12 OR2 s ! 0 2 0 1 ~635~1
- 2 - A 21 AND2 ! 0 4 0 4 :635
- 5 - A 03 OR2 s 1 3 0 1 ~641~1
- 4 - A 08 OR2 s 1 2 0 1 ~641~2
- 6 - A 08 OR2 s 1 2 0 1 ~641~3
- 7 - A 08 OR2 1 2 0 1 :641
- 4 - A 21 OR2 s 1 3 0 1 ~642~1
- 5 - A 21 OR2 s 1 2 0 1 ~642~2
- 8 - A 21 OR2 s 1 2 0 1 ~642~3
- 7 - A 22 OR2 1 2 0 1 :642
- 2 - A 03 OR2 s 1 3 0 1 ~643~1
- 4 - A 03 OR2 s 1 2 0 1 ~643~2
- 6 - A 17 OR2 s 1 2 0 1 ~643~3
- 7 - A 17 OR2 1 2 0 1 :643
- 1 - A 21 OR2 s 1 3 0 1 ~644~1
- 3 - A 21 OR2 s 1 2 0 1 ~644~2
- 5 - A 23 OR2 s 1 2 0 1 ~644~3
- 6 - A 23 OR2 1 2 0 1 :644
- 7 - A 03 AND2 1 1 0 1 :657
- 6 - A 21 AND2 1 1 0 1 :658
- 7 - A 18 AND2 1 1 0 1 :659
- 5 - A 13 AND2 1 1 0 1 :660
- 1 - A 03 OR2 s ! 0 2 0 8 ~681~1
- 2 - A 13 AND2 ! 0 3 0 4 :681
- 2 - A 22 AND2 0 4 0 2 :684
- 5 - A 18 AND2 0 4 0 2 :685
- 7 - A 13 AND2 0 4 0 2 :686
- 8 - A 11 OR2 s 2 2 0 1 ~687~1
- 6 - A 11 OR2 s 1 2 0 1 ~687~2
- 8 - A 03 OR2 s 1 3 0 1 ~687~3
- 3 - A 03 OR2 1 3 0 1 :687
- 7 - A 11 OR2 s 2 2 0 1 ~688~1
- 1 - A 11 OR2 s 1 2 0 1 ~688~2
- 5 - A 22 OR2 s 1 3 0 1 ~688~3
- 6 - A 22 OR2 1 3 0 1 :688
- 3 - A 11 OR2 s 2 2 0 1 ~689~1
- 5 - A 11 OR2 s 1 2 0 1 ~689~2
- 8 - A 18 OR2 s 1 3 0 1 ~689~3
- 6 - A 18 OR2 1 3 0 1 :689
- 3 - A 19 OR2 s 2 2 0 1 ~690~1
- 7 - A 19 OR2 s 1 2 0 1 ~690~2
- 4 - A 13 OR2 s 1 3 0 1 ~690~3
- 4 - A 23 OR2 1 3 0 1 :690
- 6 - A 03 AND2 0 4 0 2 :728
- 8 - A 19 OR2 s 2 2 0 1 ~732~1
- 1 - A 19 OR2 s 1 2 0 1 ~732~2
- 1 - A 08 OR2 s 1 2 0 1 ~732~3
- 2 - A 08 OR2 s 2 2 0 1 ~732~4
- 4 - A 11 OR2 s 2 2 0 1 ~733~1
- 2 - A 11 OR2 s 1 2 0 1 ~733~2
- 1 - A 22 OR2 s 1 2 0 1 ~733~3
- 7 - A 21 OR2 s 2 2 0 1 ~733~4
- 5 - A 19 OR2 s 2 2 0 1 ~734~1
- 4 - A 19 OR2 s 1 2 0 1 ~734~2
- 1 - A 17 OR2 s 1 2 0 1 ~734~3
- 2 - A 17 OR2 s 2 2 0 1 ~734~4
- 2 - A 19 OR2 s 2 2 0 1 ~735~1
- 6 - A 19 OR2 s 1 2 0 1 ~735~2
- 1 - A 23 OR2 s 1 2 0 1 ~735~3
- 2 - A 23 OR2 s 2 2 0 1 ~735~4
- 3 - A 08 OR2 0 4 0 1 :736
- 3 - A 22 OR2 0 4 0 1 :737
- 3 - A 17 OR2 0 4 0 1 :738
- 3 - A 23 OR2 0 4 0 1 :739
- 8 - A 08 OR2 s 2 2 0 1 ~740~1
- 8 - A 22 OR2 s 2 2 0 1 ~741~1
- 8 - A 17 OR2 s 2 2 0 1 ~742~1
- 8 - A 23 OR2 s 2 2 0 1 ~743~1
- 5 - A 08 DFFE + 1 3 1 2 :744
- 4 - A 22 DFFE + 1 3 1 2 :745
- 5 - A 17 DFFE + 1 3 1 2 :746
- 7 - A 23 DFFE + 1 3 1 2 :747
- 2 - A 04 OR2 ! 3 0 0 1 :784
- 3 - A 04 OR2 3 1 0 1 :798
- 4 - A 04 OR2 3 1 0 1 :825
- 5 - A 04 OR2 3 1 0 1 :854
- 7 - A 04 OR2 0 4 0 1 :879
- 4 - A 18 OR2 3 1 0 1 :1021
- 3 - A 13 OR2 3 1 0 1 :1052
- 1 - A 13 AND2 0 4 0 1 :1064
- 3 - A 18 AND2 0 4 0 1 :1065
- 6 - A 13 DFFE + 2 2 1 1 :1285
- 2 - A 18 DFFE + 2 2 1 1 :1286
- 6 - A 04 DFFE + 0 3 1 0 :1287
- 8 - A 04 DFFE + 0 3 1 0 :1288
- 1 - A 04 DFFE + 0 3 1 0 :1289
- 4 - A 12 DFFE + 0 3 1 1 :1290
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 54/ 96( 56%) 30/ 48( 62%) 34/ 48( 70%) 14/16( 87%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 4/ 48( 8%) 1/ 48( 2%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 2/ 96( 2%) 1/ 48( 2%) 2/ 48( 4%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
08: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
12: 4/24( 16%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
16: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
17: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
19: 4/24( 16%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clk
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** EQUATIONS **
ahour0 : INPUT;
ahour1 : INPUT;
ahour2 : INPUT;
ahour3 : INPUT;
ahour4 : INPUT;
ahour5 : INPUT;
ahour6 : INPUT;
ahour7 : INPUT;
amin0 : INPUT;
amin1 : INPUT;
amin2 : INPUT;
amin3 : INPUT;
amin4 : INPUT;
amin5 : INPUT;
amin6 : INPUT;
amin7 : INPUT;
clk : INPUT;
clk_4Hz : INPUT;
day0 : INPUT;
day1 : INPUT;
day2 : INPUT;
day3 : INPUT;
day4 : INPUT;
day5 : INPUT;
day6 : INPUT;
day7 : INPUT;
disp_mode0 : INPUT;
disp_mode1 : INPUT;
hour0 : INPUT;
hour1 : INPUT;
hour2 : INPUT;
hour3 : INPUT;
hour4 : INPUT;
hour5 : INPUT;
hour6 : INPUT;
hour7 : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min4 : INPUT;
min5 : INPUT;
min6 : INPUT;
min7 : INPUT;
mon0 : INPUT;
mon1 : INPUT;
mon2 : INPUT;
mon3 : INPUT;
mon4 : INPUT;
mon5 : INPUT;
mon6 : INPUT;
mon7 : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec4 : INPUT;
sec5 : INPUT;
sec6 : INPUT;
sec7 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
week0 : INPUT;
week1 : INPUT;
week2 : INPUT;
week3 : INPUT;
year0 : INPUT;
year1 : INPUT;
year2 : INPUT;
year3 : INPUT;
year4 : INPUT;
year5 : INPUT;
year6 : INPUT;
year7 : INPUT;
-- Node name is 'scan_data0'
-- Equation name is 'scan_data0', type is output
scan_data0 = _LC7_A23;
-- Node name is 'scan_data1'
-- Equation name is 'scan_data1', type is output
scan_data1 = _LC5_A17;
-- Node name is 'scan_data2'
-- Equation name is 'scan_data2', type is output
scan_data2 = _LC4_A22;
-- Node name is 'scan_data3'
-- Equation name is 'scan_data3', type is output
scan_data3 = _LC5_A8;
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC4_A12;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC1_A4;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC8_A4;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC6_A4;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC2_A18;
-- Node name is 'scan_en6'
-- Equation name is 'scan_en6', type is output
scan_en6 = _LC6_A13;
-- Node name is ':607' = 'state0'
-- Equation name is 'state0', location is LC3_A12, type is buried.
state0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC2_A12 & _LC8_A12
# _LC4_A17 & !state0;
-- Node name is ':606' = 'state1'
-- Equation name is 'state1', location is LC6_A1, type is buried.
state1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC8_A12 & _LC8_A13
# _LC4_A1;
-- Node name is ':605' = 'state2'
-- Equation name is 'state2', location is LC8_A1, type is buried.
state2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC5_A1
# !_LC1_A3 & _LC8_A12
# _LC2_A1 & _LC8_A12;
-- Node name is ':89'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = LCELL( _EQ004);
_EQ004 = !state0 & state1 & state2
# !state0 & !state1 & !state2;
-- Node name is ':119'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ005);
_EQ005 = state0 & !state1 & !state2;
-- Node name is ':144'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = LCELL( _EQ006);
_EQ006 = !state0 & state1 & !state2;
-- Node name is ':169'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ007);
_EQ007 = state0 & state1 & !state2;
-- Node name is ':194'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ008);
_EQ008 = !state0 & !state1 & state2;
-- Node name is ':219'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ009);
_EQ009 = state0 & !state1 & state2;
-- Node name is ':245'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ010);
_EQ010 = _LC7_A12
# _LC2_A1
# _LC1_A1;
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