📄 scan_disp.rpt
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Project Information e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/23/2005 17:35:11
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
scan_disp
EPF10K10TC144-3 74 10 0 0 0 % 103 17 %
User Pins: 74 10 0
Project Information e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
** FILE HIERARCHY **
|lpm_add_sub:1291|
|lpm_add_sub:1291|addcore:adder|
|lpm_add_sub:1291|altshift:result_ext_latency_ffs|
|lpm_add_sub:1291|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1291|altshift:oflow_ext_latency_ffs|
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
***** Logic for device 'scan_disp' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** ERROR SUMMARY **
Info: Chip 'scan_disp' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
c
a a G l V a
w h h G V a h y G h N k C a y V a h h
e m o d o N m m m m C m m o e N o D s _ s C m m m e m s d C m o d o d m
e o u a u D i i o i C i o u a D u I e 4 e I o i i a o e a C i u a u a i
k n r y r I n n n n I n n r r I r N l H l N n n n r n c y I n r y r y n
0 0 6 4 1 O 6 3 4 4 O 2 5 4 5 O 6 T 0 z 1 T 3 3 2 7 2 6 1 O 7 3 2 7 6 7
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
min5 | 7 102 | min0
day0 | 8 101 | sec4
year2 | 9 100 | year4
scan_data2 | 10 99 | year1
amin0 | 11 98 | sec5
week2 | 12 97 | amin5
scan_data0 | 13 96 | hour5
sec7 | 14 95 | ahour1
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | scan_en2
RESERVED | 19 EPF10K10TC144-3 90 | scan_en1
RESERVED | 20 89 | scan_data3
scan_data1 | 21 88 | RESERVED
RESERVED | 22 87 | scan_en4
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
scan_en5 | 28 81 | RESERVED
hour4 | 29 80 | RESERVED
RESERVED | 30 79 | scan_en3
scan_en6 | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
min1 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
hour0 | 36 73 | mon1
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
s s w G h m y a V a a a y G s V V d c d G G d d V w h y a G s a m d V a
e e e N o o e h C h m m e N e C C i l i N N a a C e o e m N e h o a C h
c c e D u n a o C o i i a D c C C s k s D D y y C e u a i D c o n y C o
0 3 k I r 6 r u I u n n r I 1 I I p p I I 7 5 I k r r n I 2 u 7 3 I u
1 O 2 0 r O r 6 4 6 O N N _ _ N N O 3 3 3 1 O r O r
0 2 T T m m T T 7 5
o o
d d
e e
0 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
A3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 16/22( 72%)
A4 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
A8 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 18/22( 81%)
A11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 15/22( 68%)
A12 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
A13 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 13/22( 59%)
A17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 16/22( 72%)
A18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 16/22( 72%)
A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 15/22( 68%)
A21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 14/22( 63%)
A22 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 18/22( 81%)
A23 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 19/22( 86%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 78/96 ( 81%)
Total logic cells used: 103/576 ( 17%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.48/4 ( 87%)
Total fan-in: 359/2304 ( 15%)
Total input pins required: 74
Total input I/O cell registers required: 0
Total output pins required: 10
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 103
Total flipflops required: 13
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 47/ 576 ( 8%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 8 8 0 0 0 8 0 0 8 7 0 8 0 0 0 8 8 8 0 8 8 8 0 103/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 8 8 0 0 0 8 0 0 8 7 0 8 0 0 0 8 8 8 0 8 8 8 0 103/0
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - 18 INPUT 0 0 0 1 ahour0
95 - - A -- INPUT 0 0 0 1 ahour1
46 - - - 17 INPUT 0 0 0 1 ahour2
113 - - - 03 INPUT 0 0 0 1 ahour3
131 - - - 15 INPUT 0 0 0 1 ahour4
72 - - - 04 INPUT 0 0 0 1 ahour5
142 - - - 23 INPUT 0 0 0 1 ahour6
68 - - - 07 INPUT 0 0 0 1 ahour7
11 - - A -- INPUT 0 0 0 1 amin0
65 - - - 09 INPUT 0 0 0 1 amin1
133 - - - 17 INPUT 0 0 0 1 amin2
121 - - - 10 INPUT 0 0 0 1 amin3
48 - - - 15 INPUT 0 0 0 1 amin4
97 - - A -- INPUT 0 0 0 1 amin5
47 - - - 16 INPUT 0 0 0 1 amin6
114 - - - 04 INPUT 0 0 0 1 amin7
55 - - - -- INPUT G 0 0 0 0 clk
125 - - - -- INPUT 0 0 0 6 clk_4Hz
8 - - A -- INPUT 0 0 0 1 day0
116 - - - 05 INPUT 0 0 0 1 day1
112 - - - 03 INPUT 0 0 0 1 day2
70 - - - 05 INPUT 0 0 0 1 day3
141 - - - 22 INPUT 0 0 0 1 day4
60 - - - 12 INPUT 0 0 0 1 day5
110 - - - 01 INPUT 0 0 0 1 day6
59 - - - 12 INPUT 0 0 0 1 day7
54 - - - -- INPUT 0 0 0 9 disp_mode0
56 - - - -- INPUT 0 0 0 8 disp_mode1
36 - - - 24 INPUT 0 0 0 1 hour0
140 - - - 21 INPUT 0 0 0 1 hour1
41 - - - 20 INPUT 0 0 0 1 hour2
63 - - - 11 INPUT 0 0 0 1 hour3
29 - - C -- INPUT 0 0 0 1 hour4
96 - - A -- INPUT 0 0 0 1 hour5
128 - - - 13 INPUT 0 0 0 1 hour6
111 - - - 02 INPUT 0 0 0 1 hour7
102 - - A -- INPUT 0 0 0 1 min0
33 - - C -- INPUT 0 0 0 1 min1
120 - - - 09 INPUT 0 0 0 1 min2
137 - - - 19 INPUT 0 0 0 1 min3
135 - - - 18 INPUT 0 0 0 1 min4
7 - - A -- INPUT 0 0 0 1 min5
138 - - - 20 INPUT 0 0 0 1 min6
109 - - - 01 INPUT 0 0 0 1 min7
143 - - - 24 INPUT 0 0 0 1 mon0
73 - - - 02 INPUT 0 0 0 1 mon1
118 - - - 07 INPUT 0 0 0 1 mon2
122 - - - 12 INPUT 0 0 0 1 mon3
136 - - - 19 INPUT 0 0 0 1 mon4
132 - - - 16 INPUT 0 0 0 1 mon5
42 - - - 19 INPUT 0 0 0 1 mon6
69 - - - 06 INPUT 0 0 0 1 mon7
37 - - - 23 INPUT 0 0 0 1 sec0
51 - - - 13 INPUT 0 0 0 1 sec1
67 - - - 08 INPUT 0 0 0 1 sec2
38 - - - 22 INPUT 0 0 0 1 sec3
101 - - A -- INPUT 0 0 0 1 sec4
98 - - A -- INPUT 0 0 0 1 sec5
117 - - - 06 INPUT 0 0 0 1 sec6
14 - - A -- INPUT 0 0 0 1 sec7
126 - - - -- INPUT 0 0 0 6 sel0
124 - - - -- INPUT 0 0 0 6 sel1
144 - - - 24 INPUT 0 0 0 1 week0
39 - - - 21 INPUT 0 0 0 1 week1
12 - - A -- INPUT 0 0 0 1 week2
62 - - - 11 INPUT 0 0 0 1 week3
43 - - - 18 INPUT 0 0 0 1 year0
99 - - A -- INPUT 0 0 0 1 year1
9 - - A -- INPUT 0 0 0 1 year2
64 - - - 10 INPUT 0 0 0 1 year3
100 - - A -- INPUT 0 0 0 1 year4
130 - - - 14 INPUT 0 0 0 1 year5
49 - - - 14 INPUT 0 0 0 1 year6
119 - - - 08 INPUT 0 0 0 1 year7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\amj\eda\experiment\calendar_clock\scan_disp.rpt
scan_disp
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
13 - - A -- OUTPUT 0 1 0 0 scan_data0
21 - - B -- OUTPUT 0 1 0 0 scan_data1
10 - - A -- OUTPUT 0 1 0 0 scan_data2
89 - - B -- OUTPUT 0 1 0 0 scan_data3
90 - - B -- OUTPUT 0 1 0 0 scan_en1
91 - - B -- OUTPUT 0 1 0 0 scan_en2
79 - - C -- OUTPUT 0 1 0 0 scan_en3
87 - - B -- OUTPUT 0 1 0 0 scan_en4
28 - - C -- OUTPUT 0 1 0 0 scan_en5
31 - - C -- OUTPUT 0 1 0 0 scan_en6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
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